Magnetic memory device and writing method of the same

ABSTRACT

The present invention provides a magnetic memory device based on a novel driving method realizing reliable writing and a method of writing the magnetic memory device. Four parallel portions are formed in a pair of loop-shaped write lines ( 6 Xn) and ( 6 Yn). Magnetoresistive devices ( 12 A) and ( 12 B) disposed in the parallel portion in an upper stage construct a memory cell ( 12 Ev), and magnetoresistive devices ( 12 A) and ( 12 B) disposed in the parallel portion in a lower stage construct a memory cell ( 12 Od). When current in the direction from the drive point A to the drive point B is passed from the current drives ( 123   n ) and ( 133   n ), the directions of the currents in the write lines ( 6 Xn) and ( 6 Yn) are aligned in the parallel portion of the memory cell ( 12 Ev) but are opposite to each other in the parallel portion in the memory cell ( 12 Od). In the memory cell ( 12 Ev), induced magnetic fields enhance each other, and the magnetization directions of the magneto-sensitive layers of the magnetoresistive devices ( 12 A) and ( 12 B) are anti-parallel with each other. In the memory cell ( 12 Od), the induced magnetic fields cancel each other out.

TECHNICAL FIELD

The present invention relates to a magnetic memory device constructed byusing a magnetoresistive device including a ferromagnetic material andfor writing and storing information by controlling the magnetizationdirection of the ferromagnetic material, and to a writing method of themagnetic memory device.

BACKGROUND ART

Increase in the speed of information processing in a computer, a mobilecommunication device, and the like matches the trend aiming at so-calledubiquitous computing and is becoming more and more important. Itaccompanies strong demand for development of a higher-speed nonvolatilememory. As a memory replacing a conventional flash EEPROM, a hard diskdevice, and the like, an MRAM (Magnetic Random Access Memory) isregarded as a promising memory.

In the MRAM, each of memory cells arranged in a matrix is constructed bya magnetic device. The MRAM currently used in practice utilizes thegiant magneto-resistive (GMR) effect. The GMR effect is a phenomenonsuch that in a stacked body in which two ferromagnetic layers aredisposed so that their axes of easy magnetization are aligned, in thecase where the magnetization directions of the layers are parallel withthe axis of easy magnetization, the resistance value of the stackedlayer becomes the minimum. In the case where the magnetizationdirections are anti-parallel with the axis of easy magnetization, theresistance value becomes the maximum. In each of the memory cells, bymaking the two states correspond to binary information of “0” and “1”,information is stored. By detecting the resistance which variesaccording to information as a change in current or voltage, informationis read. In an actual GMR device, two ferromagnetic layers are stackedsandwiching a nonmagnetic layer. One of the two ferromagnetic layers isa pinned layer whose magnetization direction is pinned, and the other isa free layer (magneto-sensitive layer) whose magnetization direction canchange according to an external magnetic field.

On the other hand, in a magnetic device using a tunnelingmagneto-resistive (TMR) effect, the resistance change rate can be mademuch higher than that of the GMR device. The TMR effect is a phenomenonsuch that the value of tunnel current passing through an insulatinglayer changes in accordance with relative angles of the magnetizationdirections of two ferromagnetic layers (a pinned layer and a free layer)stacked while sandwiching a very-thin insulating layer. That is, thetunnel current becomes the maximum (the resistance value of the deviceis the minimum) when the magnetization directions of the twoferromagnetic layers are parallel with each other, and becomes theminimum (the resistance value of the device is the maximum) when themagnetization directions are anti-parallel with each other. Based on theprinciple, there is a TMR device whose resistance change rate reaches40% or higher. Since the resistance of the TMR device is high, it issaid that matching with MOSFET (Metal Oxide Semiconductor Field EffectTransistor) is easy. From the above advantages, the TMR-MRAM can easilyobtain a higher output, and improvement in storage capacity and accessspeed is expected.

Those MRAMs write information by similar methods although their types ofelements are different from each other. Specifically, current is passedto a write line to introduce a magnetic field, and the magnetizationdirection of the free layer is controlled by the current magnetic field.By the control, the relative magnetization directions of theferromagnetic layers become parallel or anti-parallel with each other,and corresponding binary information is stored.

For example, a conventional TMR-MRAM has the following configuration. Asshown in FIG. 24, a bit line 201 and a write word line 202 extendinglinearly are orthogonal to each other. In an area of a dotted lineusing, as a unit, a TMR device 205 (expressed as a resistor in thecircuit) disposed at each of the intersecting areas of the bit line 201and the write word line 202, a memory cell is constructed. The bit line201 is a line commonly used for writing and reading, functions as a cellselection line in the bit direction at the time of writing, andfunctions as a sense line at the time of reading. To each of the bitlines 201, the source and drain of a bit selecting transistor 204 areconnected. Current flows to the bit line 201 only when the bit line 201is selected by a bit decode value input to the gate terminal. Similarly,current flows to the write word line 202 only when the write word line202 is selected according to a word decode value. Therefore, in aselected cell at the time of writing, current flows in both of the bitline 201 and the write word line 202.

For reading operation, one end of the TMR device 205 is connected to thebit line 201, and the other end is grounded via a cell selectingtransistor 206. The gate terminal of the cell selecting transistor 206is connected in parallel with a read word decode line 203 provided foreach cell word line. Therefore, in a selected cell at the time ofreading, sensing current supplied from the bit line 201 passes throughthe TMR device 205 and the cell selecting transistor 206 and flows tothe ground.

FIG. 25 shows a sectional structure of a memory cell seen from thedirection of the arrow A in FIG. 24. The TMR device 205 is a stackedbody of a pinned layer 207, an insulating layer 208, and a free layer209. The magnetization of the pinned layer 207 is fixed in the directionshown in the diagram, and the magnetization of the free layer 209 can beinverted in both of the directions shown in the diagram. A write stateof the TMR device 205 is determined by the relative magnetizationdirections of the free layer 209 and the pinned layer 207, that is, themagnetization direction of the free layer 209. However, conventionally,at the time of writing, current is passed to the bit line 201 and thewrite word line 202 to induce the magnetic fields into two directions tothe free layer 209.

The operation is based on the theory of switching magnetic fields, inwhich when a synthetic magnetic field vector of magnetic fields Hx andHy exceeds the region specified by a closed curve (so-called asteroidcurve) shown in FIG. 26, the magnetization direction of the free layer209 can be changed by the synthetic magnetic field. The free layer 209in this case is a thin film having uniaxial magnetic anisotropy and hasa single magnetic domain structure. It is assumed that magnetizationinversion occurs by simultaneous turn. The magnetic fields Hx and Hy aremagnetic field components in the direction of the axis of hardmagnetization and the direction of the axis of easy magnetization of thefree layer 209. When the synthetic magnetic field is applied in thedirection at the angle φ with respect to the axis of easy magnetizationin the film surface of the free layer 209, the magnetization is at theangle satisfying 0<θ<φ at which torque received from the magnetic fieldand torque toward the axis of easy magnetization by magnetic anisotropyare equal to each other. The critical magnetic field in magnetizationswitching is expressed by the curve of FIG. 26 (Hsw denotes thethreshold of the application magnetic field which enables magnetizationinversion). The process of specifying each of the directions of matrixelectrode wiring by inputting an address and unconditionally selecting adesired cell is according to the principle of the matrix driving method.

In the matrix driving method, generally, auxiliary cell selection thatmakes a predetermined cell line half-selected is performed by using aselection line. By giving a data signal exceeding an operation thresholdto a data line, a single cell is selected from the half-selected cells.The state is controlled according to data. Memories other than the MRAMand a digitally-driven display are also designed on the basis of such anoperation principle. With respect to this point as well, a conventionalMRAM is not exceptional but is driven based on a similar principle.Specifically, current is passed in the direction of blank arrows inFIGS. 24 and 25 to the bit line 201 to make the bias magnetic fields Hxgenerate in a predetermined direction, and a corresponding bit line ishalf-selected. On the other hand, current is passed in the directionaccording to data out of the both directions to the write word line 202to make the magnetic fields Hy or the inversion magnetic fields −Hycorresponding to the magnetization direction of the free layer 209generate. In such a manner, the magnetization direction controlaccording to data is selectively performed on a cell in thecorresponding word line in the half-selected bit line.

Since the bit line 201 is used for detecting weak voltage or current asa sense line at the time of reading, it is designed as a common linewhose current permission value is small. The amount of current passed atthe time of writing is also small. That is, the magnetic field Hx isrelatively small and is regarded as a bias magnetic field whosedirection is fixed and which is applied for selecting a cell.

On the other hand, in recent years, cell structures aiming atimprovement in write efficiency have been proposed. For example, asshown in FIG. 27, a technique of introducing a closed magnetic circuitstructure to a memory cell 211 to reduce the influence of ademagnetizing field at an end of a free layer 214 and stabilize themagnetization of the memory cell 211 is disclosed (refer to JapanesePatent Laid-Open No. 2001-273759). The memory cell 211 has a pinnedlayer 212, an insulating layer 213, the free layer 214, and a closedmagnetic circuit layer 215 which are stacked. The closed magneticcircuit layer 215 promotes magnetization inversion of the free layer 214and also contributes to stabilize the magnetization against an externalleak magnetic field. Therefore, reduction in size of the memory cell 211can be realized. For example, a technique of bending write lines asshown in FIG. 28 to shorten the minimum cycle of the write lines,thereby realizing higher packing density is proposed. In the diagram, aword line 217 has a linear shape and a bit line 216 is bent.

A similar wiring structure is also disclosed in Japanese PatentLaid-Open No. 2002-289807 (FIG. 29). In this case, a write line 221 isbent with a wiring width of “a” and a bent-portion length of “b”, andthe relative directions of write current flowing in the portion andwrite current in the write line 222 are controlled. In such a manner, asshown in FIG. 30, an induced magnetic field H1 by the write current inthe write line 221 is generated at an angle θ=tan⁻¹ (b/a) relative to aninduced magnetic field H2 by the write current in the write line 222 inorder to make a resultant vector H12 of the magnetic fields H1 and H2larger than that in the case where the magnetic fields are orthogonal toeach other.

The inventors of the present invention, however, have noticed that if aconventional wiring structure and a convention writing method areemployed in the case of disposing write lines in the memory cells almostparallel to each other as described above, there is the possibility thatreliable writing is not performed.

In a conventional MRAM circuit, since it is necessary to pass writecurrent in the inverted direction in accordance with data to the writeword line 202, by giving a positive pulse or negative pulse, current canbe passed in both directions. In contrast, to the bit line 201, writecurrent is supplied only in one direction to give the fixed biasmagnetic field Hy. Moreover, the bit line 201 has the structure in whichcurrent can be passed always only in one direction (the direction of theblank arrows in FIGS. 24 and 25).

If a negative pulse voltage is applied to the bit line 201 to passcurrent in the direction opposite to that shown by the blank arrow inFIG. 24, the current passes through the cell selection transistor 206 ofeach of cells connected to the bit line 201. Specifically, the cellselection transistor 206 is generally an enhancement-mode MOS transistorand the gate voltage of the cell selection transistor 206 in an offstate for writing operation is supposed to be 0V or negative potentialat this time. If the negative pulse is applied to the drain side in thiscase, since the gate has the same potential of 0V as that on the sourceside or a higher potential, the inherent function of the source and thatof the drain are reversed, and current flows from the source to thedrain.

When the magnetic fields H1 and H2 are applied as shown in FIG. 30 byapplying such a conventional circuit configuration and a conventionaldriving method, as shown in FIG. 31, an inverted magnetic field vector−H12 obtained by the magnetic fields H1 and −H2 is not symmetrical withthe magnetic field vector H12 with respect to the axis of easymagnetization of the free layer 209, and the magnitude of the invertedmagnetic field vector −H12 is smaller than that of the magnetic fieldvector H12. Consequently, binary information cannot to be written in anequivalent state and, moreover, there is the possibility that binaryinformation cannot be written reliably.

As described above, even if the structure of the write line is improved,when the improved structure is simply fit in a conventional circuitconfiguration, the resultant structure cannot be practically used. Onthe other hand, under present circumstances, improvement in a wholeconfiguration of a circuit has not been progressed and the configurationof the MRAM and the principle of driving have not been largely changedfrom the conventional ones. In view of the circumstances, the inventorsof the present invention have concluded that it is necessary to improvean MRAM as a memory which can be actually driven and, for this purpose,to improve not only a write line in a conventional circuit but also awhole memory structure including a read circuit system in order toachieve the object.

DISCLOSURE OF THE INVENTION

The present invention has been achieved in consideration of the problemsand an object of the invention is to provide a magnetic memory devicebased on a novel driving method realizing reliable writing operation anda writing method of the magnetic memory device.

A magnetic memory device of the preset invention includes: a read lineto which read current is passed; first and second write lines disposedseparately from the read line so that write current can be passed in twoways to each of the first and second write lines, where a parallelportion in which the first and second write lines extend parallel witheach other is formed by bending at least one of the first and secondwrite lines; and a magnetoresistive device having a magneto-sensitivelayer whose magnetization direction changes according to a magneticfield applied, and disposed in the parallel portion. At least one of thefirst and second write lines is formed in a loop shape so as to includea bent portion and first and second portions connecting the bent portionand both ends, the magnetization direction of the magneto-sensitivelayer changes according to a magnetic field generated by write currentflowing in the parallel portion, and information is written.

In the magnetic memory device, the write line is provided perfectlyseparate from the read line, so that current can be passed in two waysin both of the first and second write lines. At least one of the writelines is formed in a loop shape by being bent between a first portionand a second portion, and current is circulated. Therefore, currentshaving the same magnitude and in opposite directions flow in the firstand second portions. Further, at least one of the first and second writelines is bent so as to form plural parallel portions extending inparallel with each other, and magnetoresistive devices are disposed inthe parallel portions. That is, by supplying the write currentcontrolled in two ways to each of the first and second write lines, thedirections of the write currents are aligned in the parallel portionsand magnetic fields are generated so as to enhance each other. Accordingto the application magnetic fields, the magnetization directions of themagneto-sensitive layers change. In this case, since at least one of thewrite lines is formed in a loop shape, plural parallel portions in whichthe first and second write lines are the same are formed. Therefore, themagnetoresistive device is disposed in a position so that it can beunconditionally selected in correspondence with the direction of thewrite current and operate properly, and a binary state can be writtenwith reliability. Expression “write lines are parallel with each other”in the present invention includes an error range of ±10° in manufacture.

In the wiring structure of the write line, preferably, (1) the parallelportion is formed by bending one of the first and second portions of thewrite line into a rectangular wave shape or a trapezoid wave shape, or(2) the parallel portion is formed by bending both of the first andsecond portions into a rectangular wave shape or a trapezoid wave shape.When the write line is bent in the rectangular wave shape or thetrapezoid wave shape, the parallel portion is efficiently provided, andthe write currents are supplied in opposite directions to theneighboring magnetoresistive devices from the write line bent. In thecase of forming the parallel portion by bending both of the first andsecond portions of the write line, more preferably, the direction ofbending the first portion and that of the second portion coincide witheach other. At this time, currents flow in opposite directions in theparallel portion in the first portion and the parallel portion in thesecond portion which face each other.

In such a magnetic memory device, preferably, one memory cell isconstructed by a pair of magnetoresistive devices. That is, one-unitinformation is stored by using two magnetoresistive devices each capableof storing one-unit information. In this case, information written inthe memory cell can be read by a differential reading method.

In the magnetic memory device, preferably, both of the first and secondwrite lines are formed in a loop shape, one of the first and secondwrite lines is bent so that both of the first and second portions have arectangular wave shape or a trapezoid wave shape, and the bendingdirection of the first portion and that of the second portion coincidewith each other, thereby forming four parallel portions in a pair offirst and second write lines. A pair of magnetoresistive devicesdisposed in the two parallel portions provided in the first portionconstruct a memory cell belonging to a first group, and a pair ofmagnetoresistive devices disposed in the two parallel portions providedin the second portion construct a memory cell belonging to a secondgroup. As described above, when both of the first and second write linesare formed in a loop shape and bent as described above, two parallelportions are formed in each of the first and second portions of the bentwrite line in the pair of first and second write lines. In this case,each of a pair of magnetoresistive devices disposed in each of theparallel portions in the first portion and a pair of magnetoresistivedevices disposed in each of the parallel portions in the second portioncan be operated separately as a memory cell. Further, a plurality ofmemory cells are formed by combinations of the first and second writelines. By setting memory cells provided in the first portion into afirst group and setting memory cells provided in the second portion intoa second group, one memory cell can be selected.

For this purpose, it is preferable to provide a write logic controllerfor receiving address information indicating the first or second groupto which a memory cell to be written belongs and write information to bewritten, and selecting the direction of write current supplied to thefirst and second write lines on the basis of the address information andthe write information. In the configuration, the memory cells in thefirst portion and the memory cells in the second portion use the samelooped write line. According to a memory cell to be written, thedirection of the write current supplied to the first and second writelines varies. Naturally, the direction of the write current also variesaccording to data to be written. The write logic controllerunconditionally determines the direction of write current supplied tothe first and second write lines from the two conditions and outputs theresultant.

Preferably, the magnetic memory device further comprises a write currentdrive circuit including: a current direction controller to which bothends of a write line having a loop shape as one of the first and secondwrite lines are connected and which controls the direction of the writecurrent in the write line in two ways; and a current amount controllerfor controlling the amount of write current in the write line to aconstant value, and supplying the write current to the write line. Whensuch a write current drive circuit is used, by the current directioncontroller, the direction of the write current is switched in two waysso that current flows in one of both ends of the write line and flowsout from the other end and, by the current amount controller, thecurrent amount is controlled to be always constant for a period sincethe current flows in the write line until the current flows out from thewrite line. In the magnetic memory device of the preset invention,“connection” denotes at least electric connection, but physical directconnection is not always a condition. In the expression of “controllingthe amount of write current to a constant value” in the invention, awrite current amount before the write line or at the inflow end is notthe target to be controlled, but it denotes a constant current controlfor controlling the magnitude of the write current to a constant valuefor the entire write line since the write current flows from an end ofthe write line until the write current flows out from the other end.

The write current drive circuit is preferably controlled by the writelogic controller. That is, the magnetic memory device further comprisesa write current drive circuit, the direction of the write currentsupplied to the first and second write lines selected by the write logiccontroller is output as direction control information for controllingthe current direction to the current direction controller, and thecurrent direction controller controls the direction of the write currentin the write line on the basis of the direction control information.

Concretely, the current direction controller includes: a firstdifferential switch pair constructed by first and second currentswitches provided for both ends of the write line and operating so thatone of the first and second current switches is open and the other isclose; and a second differential switch pair constructed by third andfourth current switches provided in correspondence with the first andsecond current switches, respectively, and operating so that one of thethird and fourth current switches is open and the other is close. Thefirst differential switch pair has the function of selecting one of bothends of the write line as a write current inflow side, and the seconddifferential switch pair has the function of selecting the other one ofthe both ends of the write line as a write current outflow side. Theopen/close state (on/off state) in a general switching element assumesthe case where the conductive state (or the state where the amount ofcurrent flowing is equal to or larger than a threshold value) is the onstate, and a substantial shield state in which current is hardly passed(or the amount of current flowing is less than a threshold value). Theon and off states in this case are specified stationarily and each ofthe states can be digitally identified. In contrast, the “open/closestate (on/off state)” of the current switch in the present invention isa concept including not only the two states but also relative two stateswhich occur in the differential operation by the current switches pairedas a differential switch pair; the on state in which a larger amount ofcurrent is passed and the off state in which a smaller amount of currentis passed.

In the current direction controller, the first current switch and thesecond current switch in the first differential switch pair are inopen/close states (on/off states) opposite to each other. At both endsof the write line, the side on which the corresponding current switch ison is conducted so that current is permitted to flow, but the side onwhich the corresponding current switch is off is blocked so that nocurrent flows. Consequently, the side on which control is performed bythe on-state current switch in the first differential switch pair out ofboth ends of the write line is selected as the write current inflowside. In the second differential switch pair, the third current switchis provided in correspondence with one end of the write line in a mannersimilar to the first current switch, and the fourth current switch isprovided in correspondence with the other end of the write line in amanner similar to the second current switch. The third and fourthcurrent switches are in the operation states opposite to each other, andthe second differential switch pair acts in a manner similar to thefirst differential switch pair. Consequently, the side on which controlis performed by the on-state current switch in the second differentialswitch pair out of both ends of the write line is selected as the writecurrent outflow side. In such a manner, in the current directioncontroller, the direction of the write current is unconditionallydetermined.

To make the first and second differential switch pairs cooperate witheach other to select the different sides of the write line, for example,the current direction controller may include a differential controllerfor performing a control so that the first and fourth current switchesare in the same open/close state, and the second and third currentswitches are in the state opposite to the state of the first and fourthcurrent switches.

In such a magnetic memory device, preferably, magnetic fields generatedby the write current supplied to the first and second write lines areapplied to the magneto-sensitive layer so as to be in the same directionin the memory cell to be written. For example, by disposing themagnetoresistive device in an area where a magnetic field is generatedonly in a direction orthogonal to the parallel portion, in the parallelportion of the write lines, the magnetic fields induced to the writecurrent can be made parallel with each other and their directions can bealigned in a single direction. When a magnetoresistive device becomes anobject to be written, current is supplied so that the directions arealigned in the parallel portion where the magnetoresistive device isdisposed. The direction of the magnetic field generated at this time isthe magnetization inversion direction itself, and it means that thefirst and second write lines are driven to induce the magnetic fields inthe direction corresponding to information. By making the magnitudes ofthe magnetic fields generated in the first and second write lines equalto each other, in the case where the directions are aligned in theparallel portion and the magnetic fields enhance each other, writing isenabled. In the case where the directions are opposite to each other andthe magnetic fields cancel each other out, writing is disenabled. Byusing the phenomenon, driving control of selecting a cell to be writtenis performed.

Preferably, the magnetoresistive device in the magnetic memory devicefurther comprises a stacked body including the magneto-sensitive layer,and a toroidal magnetic layer is provided on one of the faces of thestacked body. The toroidal magnetic layer uses a direction along thestacked face as an axial direction, and the parallel portion of thefirst and second write lines penetrates the toroidal magnetic layeralong the axial direction. The expression “toroidal” in the “toroidalmagnetic layer” shows a state where, when seen at least from the writelines penetrating the toroidal magnetic layer, the magnetic layercompletely surrounds the write lines so as to be continuous magneticallyand electrically, and the section in the direction crossing the writelines is closed. Therefore, the toroidal magnetic layer may contain aninsulator as long as it is continuous magnetically and electrically, andmay include an oxide film that is generated in a manufacturing process.The “axial direction” denotes an opening direction when attention ispaid to the toroidal magnetic layer single body, that is, the directionof extension of the write line penetrating the layer. Further, theexpression “an toroidal magnetic layer is provided on one of the facesof the stacked body” includes not only the case where the toroidalmagnetic layer is disposed as a member separate from the stacked body onthe side of one of faces of the stacked body but also the case where thetoroidal magnetic layer is disposed so as to include part of the stackedbody. In such a magnetoresistive device, when current flows in the writeline, a closed magnetic circuit is formed in the toroidal magneticlayer. Thus, magnetization inversion of the magneto-sensitive layer isperformed efficiently.

In a method of writing a magnetic memory device of the invention, firstand second write lines are provided separately from a read line, andwrite current can be passed in two ways. At least one of the first andsecond write lines is formed in a loop shape including first and secondportions connecting a bent portion and both ends. A parallel portion inwhich the first and second write lines extend parallel with each otheris formed by bending at least one of the first and second write linesand making the first and second write lines cross each other. Themagnetoresistive device is disposed in the parallel portion. Writecurrent is supplied to the first and second write lines so that both ofthe write currents flowing in the first and second write lines in theparallel portion are in one of first and second directions correspondingto write information. By changing the magnetization direction of themagneto-sensitive layer by a magnetic field generated by the writecurrents, information is written.

In the method of writing a magnetic memory device according to theinvention, first, by providing the first and second write linesseparately from the read line, current is passed in two ways. Further, aparallel portion in which the write lines extend parallel with eachother has to be formed by forming at least one of the write lines in aloop shape and bending at least one of the write lines. To themagnetoresistive device disposed in the parallel portion, write currentis supplied in the direction according to information to be written asone of the two ways to both of the first and second write lines. Themagnetization direction of the magneto-sensitive layer is changed by themagnetic field induced to the write current, and information is written.

To be more concrete, preferably, two magnetoresistive devices aredisposed in a pair of the parallel portions, write current is suppliedto the first and second write lines so that the directions coincide ineach of the pair of parallel portions and the directions in the pair ofparallel portions are opposite to each other, thereby changing themagnetization directions of magneto-sensitive layers of the twomagnetoresistive devices so as to be anti-parallel with each other, andinformation is written by using the two magnetoresistive device as onememory cell. The expression “the magnetization directions areanti-parallel with each other” includes not only the case where theangle between the magnetization directions, that is, the directions ofaverage magnetization in the magnetic layers is strictly 180° but alsothe case where the angle formed between the magnetization directions isdeviated from 180° only by a predetermined angle due to an erroroccurring in manufacture, an error which occurs because a uniaxial stateis not completely obtained, or the like. In correspondence with binaryinformation, a memory cell is controlled in one of two states; a statewhere the magnetization directions of the magneto-sensitive layers ofthe pair of magnetoresistive devices are parallel with each other, and astate where the magnetization directions are anti-parallel with eachother.

More preferably, both of the first and second write lines are formed ina loop shape, the first and second portions of one of the first andsecond write lines are bent in a rectangular wave shape or a trapezoidwave shape so that their bending directions coincide with each other,four parallel portions are provided in a pair of first and second writelines, a pair of magnetoresistive devices are disposed in two parallelportions provided in the first portion, thereby constructing a memorycell belonging to a first group. A pair of magnetoresistive devices isdisposed in two parallel portions provided in the second portion,thereby constructing a memory cell belonging to a second group. Writecurrent is supplied to the pair of first and second write lines so thatcurrent flows in the same direction in the first and second write linesin both of the two parallel portions and, moreover, current flows inopposite directions in the two parallel portions in a memory cell to bewritten as one of two memory cells belonging to the first and secondgroups. Write current is supplied to the first and second write lines soas to flow in opposite directions in both of the two parallel portionsin the other cells, thereby changing a magnetization direction of eachof the magneto-sensitive layers only in the pair of magnetoresistivedevices in one of the memory cells, and selectively writing information.

At this time, by bending the first and second portions of one of thefirst and second write lines in a rectangular wave shape or a trapezoidwave shape so that their bending directions coincide with each other,the current directions of the first and second write lines are alignedin only one of the parallel portion provided in the first portion andthe parallel portion provided in the second portion. That is, when thecurrent directions of the first and second write lines are aligned inboth of the two parallel portion in a memory cell to be written, in amemory cell which is not an object to be written, the current directionsof the first and second write liens are opposite to each other in bothof the two parallel portions. Therefore, a memory cell in the firstgroup and a memory cell in the second group are not simultaneouslyselected. Information is selectively written to one of the memory cells.To a memory cell to be written, the write current is supplied indirection opposite to each other in the two parallel portions, and themagnetization directions of the magneto-sensitive layers in the pair ofmagnetoresistive devices are changed so as to be anti-parallel with eachother.

In such a manner, preferably, the write current is supplied to a writeline formed in a loop shape as one of the first and second write lineswhile controlling the direction of write current by selecting one ofboth ends as a write current inflow side and selecting the other end asan outflow side, and controlling so that the write current flows on thewrite lines with a predetermined current value. Consequently, the writecurrent is supplied to the write lines while its magnitude and directionon the write line are controlled.

It is preferable to write information by applying magnetic fields in thesame direction to the magneto-sensitive layers. That is, the directionsof application magnetic fields are aligned in a single direction inaccordance with information to be written. In this case, the sum ofinduced magnetic fields of the first and second write lines can beregarded as a single magnetic field in the magneto-sensitive layer, andthe magnetization of the magneto-sensitive layer is inverted, so tospeak, forcedly, to the direction of the magnetic field.

Further, when magnitudes of the magnetic fields applied to themagneto-sensitive layer are equalized, in the case where the magneticfields are aligned in a single direction and enhance each other, writingis enabled. In the case where the magnetic fields are in oppositedirections and cancel each other out, writing is disabled.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a whole configuration of a magneticmemory device according to a first embodiment of the invention.

FIG. 2 is a block diagram showing the configuration of a main part ofthe magnetic memory device illustrated in FIG. 1.

FIG. 3 is a cross section showing a concrete configuration of the memorycell illustrated in FIG. 1.

FIG. 4 is a configuration diagram showing a write circuit system of themagnetic memory device illustrated in FIG. 1.

FIG. 5 is a table illustrating operations in a write logic controllerillustrated in FIG. 1.

FIG. 6 is a diagram showing a circuit configuration of the write logiccontroller illustrated in FIG. 1.

FIG. 7 is a circuit diagram of a current drive illustrated in FIG. 1.

FIG. 8 is a conceptual configuration diagram showing an actionconfiguration of the current drive illustrated in FIG. 7.

FIG. 9 is a diagram showing an operation state of each of transistorsand a write current path when an X-direction current drive illustratedin FIG. 4 operates.

FIG. 10 is a diagram illustrating operation performed at the time ofwriting “1” into a memory cell in an even-numbered address in the writecircuit system of FIG. 4.

FIG. 11 is a cross section showing a storing state in which data iswritten in the memory cell illustrated in FIG. 10.

FIG. 12 is a diagram showing operation performed at the time of writing“0” into the memory cell in an even-numbered address in the writecircuit system of FIG. 4.

FIG. 13 is a cross section showing another storing state in which datais written in the memory cell illustrated in FIG. 12.

FIG. 14 is a diagram showing operation performed at the time of writing“1” into the memory cell in an odd-numbered address in the write circuitsystem of FIG. 4.

FIG. 15 is a diagram showing operation performed at the time of writing“0” into the memory cell in an odd-numbered address in the write circuitsystem of FIG. 4.

FIG. 16 is a configuration diagram of a main part of a read circuitsystem of the magnetic memory device shown in FIG. 1.

FIG. 17 is a configuration diagram showing a whole read circuit systemillustrated in FIG. 16.

FIG. 18 is a block diagram showing a whole configuration of a magneticmemory device according to a second embodiment of the invention.

FIG. 19 is a block diagram showing the configuration of a main part ofthe magnetic memory device illustrated in FIG. 18.

FIG. 20 is a configuration diagram of a main part of a read circuitsystem of the magnetic memory device illustrated in FIG. 18.

FIGS. 21A and 21B are diagrams each showing a modification of a writeline in the write circuit system illustrated in FIG. 4.

FIGS. 22A and 22B are diagrams each showing a modification of the writeline in the write circuit system illustrated in FIG. 4.

FIG. 23 is a diagram showing a modification of the write line in thewrite circuit system illustrated in FIG. 4.

FIG. 24 is a diagram showing the configuration of a conventionalmagnetic memory device.

FIG. 25 is a cross section showing a concrete configuration of aconventional magnetic memory device.

FIG. 26 is a diagram illustrating a method of writing data to theconventional magnetic memory device.

FIG. 27 is a diagram showing a sectional configuration of a magneticmemory device in a modification of a conventional magnetic memorydevice.

FIG. 28 is a diagram showing a wiring structure of a write line for themagnetic memory device illustrated in FIG. 27.

FIG. 29 is a diagram showing the configuration of a write line and amagnetic storing device in a modification of a conventional magneticmemory device.

FIG. 30 is a diagram showing a method of writing data to the magneticstoring device illustrated in FIG. 29.

FIG. 31 is a diagram for explaining problems of the writing methodillustrated in FIG. 30.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the invention will now be described in detail hereinbelowby referring to the drawings.

First Embodiment

FIG. 1 is a diagram showing a whole configuration of a magnetic memorydevice according to a first embodiment of the invention. The magneticmemory device is an MRAM embodied as a so-called semiconductor memorychip and has, as main components, an address buffer 110, an x-directionperipheral drive circuit 120, a Y-direction peripheral drive circuit130, a memory cell group 140, a data buffer 150, and a control logicportion 160. The X-direction peripheral drive circuit 120 is constructedby an X-direction address decoder 121, a constant current circuit 122for reading, and an X-direction current drive 123 for writing. TheY-direction peripheral drive circuit 130 is constructed by a Y-directionaddress decoder 131, a sense amplifier 132 for reading, and aY-direction current drive 133 for writing.

FIG. 2 is a block diagram showing the configuration of a memory cellgroup, and a write circuit system and a read circuit system in theperiphery. The memory cell group 140 is constructed by arranging anumber of memory cells 12 in a word line direction (X direction) and abit line direction (Y direction) in a matrix. In the following, each ofthe columns in the memory cells 12 in the memory cell group 140 will becalled a word line, and each of the rows will be called a bit line.

First, the write circuit system will be described. Each of a write wordline 6X and a write bit line 6Y (hereinbelow, write lines 6X and 6Y) hasa loop shape. The write line 6X is bent each time it crosses the writeline 6Y to form a rectangular wave shape, thereby forming a parallelportion in which the write lines 6X and 6Y are parallel with each other.Specifically, four parallel portions are formed from a pair of writelines 6X and 6Y, and magnetoresistive devices (12A and 12B) are disposedin each of the parallel portions. Further, one memory cell 12 isconstructed by a pair of magnetoresistive devices 12A and 12Bneighboring in the word line direction, and is disposed at each of upperand lower stages of the folded write line 6X ( . . . , 6Xn, 6Xn+1, . . .).

Both ends of each write line 6X are connected to the correspondingX-direction current drive 123, and both ends of each write line 6Y areconnected to the corresponding Y-direction current drive 133. That is,the write line 6X ( . . . , 6Xn, 6Xn+1, . . . ) and the X-directioncurrent drive 123 correspond to each other in a one-to-one manner, andcorrespond to two upper and lower stages of the memory cells 12 of thewrite line 6X. On the other hand, the write line 6Y ( . . . , 6Yn,6Yn+1, . . . ) and the Y-direction current drive 133 also correspond toeach other in a one-to-one manner, and correspond to bit lines of thememory cells 12.

In the embodiment, the memory cell 12 on the upper stage side in thewrite line 6X is called a memory cell 12Ev of an even-numbered address,and the memory cell 12 on the lower stage side is called a memory cell12Od of an odd-numbered address. A drive control is performed on each ofa memory cell group Ev of even-numbered addresses and a memory cellgroup Od of odd-numbered addresses. The drive control is performed byselecting the pair of memory cells 12Ev and 12Od disposed at the upperand lower stages of the write line 6X of the same bit line, anddetermining either the memory cell group Ev or Od to which the memorycell 12 to be operated belongs.

The write lines 6X and 6Y are disposed separately from the read lines.The read lines in FIG. 2 are the sense bit decode lines 21A and 21B(hereinbelow, sense bit lines 21A and 21B) disposed for bit columns. Themagnetoresistive devices 12A are connected to the sense bit lines 21Aand the magnetoresistive devices 12B are connected to the sense bitlines 21B via read sensing conductors 11 which will be described later.The difference between sensing currents flowing in both of the lines isamplified by the sense amplifier 132.

The read circuit system is divided by the memory cell groups 12Ev and12Od, and two systems are provided. Two sense bit lines 21A and twosense bit lines 21B are provided in correspondence with the memory cellgroups 12Ev and 12Od , and are connected to sense amplifiers 132Ev and132Od, respectively. The sense amplifiers 132Ev and 132Od correspondingto the same bit columns are selected by the same bit decode value ( . .. , Yn, Yn+1, . . . ). The group of sense amplifiers 132Ev and the groupof sense amplifiers 132Od are separately cascaded and are connected to aread multiplexer 153 and an output buffer 154. One of an output of thesense amplifier 132Ev and an output of the sense amplifier 132Od isselected on the basis of an address signal A₀ of the least significantbit input from a group selection signal line 106 in the read multiplexer153. The selected sense amplifier output is output as a read data signal(Dout) from the output buffer 154.

The other components of the magnetic memory device are constructed asfollows to drive the memory cell group 140 and the peripheral circuits.

The address buffer 110 has external address input terminals A0 to A20and is connected to the X-direction address decoder 121 and theY-direction address decoder 131 via address lines 101 and 102,respectively. The address buffer 110 has the functions of receiving anaddress signal for selecting the memory cell 12 from the externaladdress input terminals A0 to A20 and amplifying the address signal to avoltage level required in the address decoders 121 and 131 by aninternal buffer amplifier. The address buffer 110 also separates theamplified selection signal into two selection signals in the word linedirection (X direction) and the bit line direction (Y direction) of thememory cell 12 and supplies the selection signals to the addressdecoders 121 and 131.

The address of the least significant bit input from the external addressinput terminal A0 is regarded as information indicating that the memorycell 12 to be selected belongs to the memory cell group Ev of aneven-numbered address or the memory cell group Od of an odd-numberedaddress. The signal voltage is set as an address selection signal A₀.Only the address selection signal A₀ is transmitted to the data buffer150 via the group selection signal line 106. In the case where themagnetic memory device has plural memory cell groups 140, an addresssignal for selecting one memory cell group 140 from the plural memorycell groups 140 is also input to the address buffer 110.

The data buffer 150 has external data terminals D0 to D7 fortransmitting/receiving digital data signals to/from the outside, and isconnected to the control logic portion 160 via a control signal line107. The data buffer 150 has, as an input system, an input buffer 151and a write logic controller 152 and has, as an output system, the readmultiplexer 153 and the output buffer 154. Each of the input buffer 151and the output buffer 154 operates according to a control signal fromthe control logic portion 160.

The input buffer 151 receives a data signal from the external dataterminals D0 to D7 at the time of writing data to the memory, amplifiesthe data signal to a voltage level required by an internal bufferamplifier, and inputs the amplified data signal to the write logiccontroller 152.

The write logic controller 152 receives the data signal from the inputbuffer 151 and the address section signal A₀ from the group selectionsignal line 106 and, on the basis of the signals, controls the operationof the current drive 123 or 133 selected by a high-order bit address.Specifically, data signals XDin and YDin and reference signals XRef andYRef are transmitted to the X-direction current drive 123 and theY-direction current drive 133 via write data buses 103 and 104,respectively, so that the current drives 123 and 133 pass current to thewrite lines 6X and 6Y in the direction according to (1) the destinationwhich is one of the pair of the memory cells 12Ev and 12Od and (2) “1”or “0” to be written.

The read multiplexer 153 is connected to the read data bus 105 and thegroup selection signal line 106 via which an output of the senseamplifier 132 and the address selection signal A₀ is input. From thesense amplifier 132, two pieces of data corresponding to both of thememory cell groups 12EV and 12Od are input. An output of the memory cell12 to be read is selected by using the address selection signal A₀ andis input to the output buffer 154. The output buffer 154 has an internalbuffer amplifier and has the function of outputting a read data signalthat is input at the time of reading data from the memory to theexternal data terminals D0 to D7 at low impedance.

The control logic portion 160 has input terminals CS and WE and isconnected to the data buffer 150 via the control signal line 107. Thecontrol logic portion 160 performs operation control on the memory cellgroup 140. From the input terminal CS, a (chip select; CS) signalindicating whether an operation of writing/reading the magnetic memorydevice is made active or not is input. From the input terminal WE, awrite enable (WE) signal for switching the writing/reading operation isinput. The control logic portion 160 has the function of amplifying asignal voltage received via the input terminal CS and WE to a voltagelevel necessary in the peripheral drive circuits 120 and 130 by theinternal buffer amplifier and transmits the amplified signal to theperipheral drive circuits 120 and 130.

Configuration of Memory Cell

FIG. 3 is a cross section showing the configuration of the memory cellaccording to the embodiment. The magnetoresistive devices 12A and 12B ofeach memory cell 12 are magnetoresistive devices using the GMR or TMReffect. As a concrete example, the case where the magnetoresistivedevices 12A and 12B are TMR devices will be described.

The memory cell 12 is constructed by the pair of right and leftmagnetoresistive devices 12B and 12A formed on a surface of a substrate10. Each of the magnetoresistive devices 12A and 12B has a configurationincluding a stacked body in which a first magnetic layer 1, anonmagnetic layer 2, and a second magnetic layer 3 are stacked, and antoroidal magnetic layer 5 disposed by using a direction along a stackedsurface as the axial direction on one of face sides of the stacked bodyand constructed so as to be penetrated by write lines 6X and 6Y in theaxial direction. The second magnetic layer 3 and the toroidal magneticlayer 5 are bonded to each other over a nonmagnetic conductive layer 4and are electrically connected to each other. Each of themagnetoresistive devices 12A and 12B is provided with the read sensingconductor 11 on the top face (face on the side opposite to the toroidalmagnetic layer 5) of the stacked body, so that current can be passedperpendicular to the stack surface of the stacked body toward thesubstrate 10.

The first magnetic layer 1 is a ferromagnetic layer whose magnetizationdirection is pinned, and the second magnetic layer 3 is a ferromagneticlayer (magneto-sensitive layer) whose magnetization direction changesaccording to an external magnetic field. The magnetic layers are stackedwhile sandwiching the nonmagnetic layer 2 which is very thin as a few nm(tens Å). In the stacked body, when a voltage in the perpendiculardirection is applied to the stack surface between the first and secondmagnetic layers 1 and 3, for example, electrons in the second magneticlayer 3 penetrate the nonmagnetic layer 2 and move in the first magneticlayer 1, so that tunnel current flows. That is, the nonmagnetic layer 2is a tunnel barrier layer in this case. The tunnel current changesaccording to relative angles between spins in the first magnetic layer 1and spins in the second magnetic layer 3 in the interface portion withthe nonmagnetic layer 2. When the spin in the first magnetic layer 1 andthat in the second magnetic layer 3 are parallel with each other, theresistance value of the magnetoresistive device 12A (12B) becomes theminimum. When they are anti-parallel with each other, the resistancevalue becomes the maximum.

The thickness of the nonmagnetic layer 2 is determined on the basis oftunnel resistance and the like. Generally, in the magnetic memory deviceusing the TMR device, for matching with a semiconductor device such as atransistor, proper tunnel resistance is tens kΩ·(μm)². To realize higherpacking density and higher operation speed in the magnetic memorydevice, the tunnel resistance is set to, preferably, 10 kΩ·(μm)² orless, more preferably, 1 kΩ·(μm)² or less. To realize such a tunnelresistance value, the thickness of the nonmagnetic layer 2 is preferablyset to 2 nm or less, more preferably, 1.5 nm or less. When thenonmagnetic layer 2 is too thin, although the tunnel resistance can bereduced, a leak current may occur due to roughness of the junctioninterface between the first and second magnetic layers 1 and 3, and theMR ratio deteriorates. To prevent this situation, the nonmagnetic layer2 has to have a thickness with which leak current does not flow.Concretely, the thickness of the nonmagnetic layer 2 is desirably 0.3 nmor more.

The magnetization direction of the second magnetic layer 3 changesaccording to an induction field that is generated when write current ispassed to the write lines 6X and 6Y and its angle relative to themagnetization of the first magnetic layer 1 is inserted. Themagnetization of the second magnetic layer 3 is inverted by using themagnetic field generated in the parallel portion of the write lines 6Xand 6Y, and these magnetic fields are directed in the same directionwith respect to the second magnetic layer 3. That is, the magneticfields generated are applied in a single direction, that is, a changedirection of the magnetization of the second magnetic layer 3, and actso as to directly determine the direction of magnetization. Themagnetoresistive device 12A (12B) is preferably disposed in an area inwhich the magnetic field is generated only in the direction orthogonalto the parallel portion in the parallel portion of the write lines 6Xand 6Y. The magnetization inversion can be realized by considering, forexample, the dimension ratio between the length of the parallel portionof the write lines 6X and 6Y and the length of the magnetoresistivedevice 12A (12B), placement on the parallel portion of themagnetoresistive device 12A (12B), and the like.

In such a manner, the magnetization direction of the second magneticlayer 3 is controlled with reliability. Since the magnitude of theapplied magnetic field is larger than combined transverse magneticfields induced to orthogonal lines, and the magnetic fields invert thedirection to the opposite direction. Consequently, in the secondmagnetic layer 3, the magnetization inversion efficiency is high and thetunnel resistance change rate higher than that in the conventionaltechnique can be obtained. Thus, the writing operation can be performedefficiently.

As described above, the magnetization direction of the second magneticlayer 3 is forcedly controlled to the direction of the magnetic fieldapplied in the parallel portion. Thus, the magnetic property can bedetermined according to the relative relation with the magnitude of theapplied magnetic field and the like. For example, when the strength ofthe applied magnetic field is sufficiently high, magnetic anisotropy inthe second magnetic layer 3 does not have to be considered. In thiscase, the invention is not limited to the single magnetic domainstructure but may have a bulk structure. In the conventional technique,writing operation is performed by using the induced magnetic fieldshaving orthogonal components. Consequently, the magneto-sensitive layerideally has uniaxial magnetic anisotropy and has to have a singlemagnetic domain. However, it is not easy to form a magneto-sensitivelayer having a single magnetic domain from a thin magnetic layer.Further, in order to control magnetic anisotropy of themagneto-sensitive layer, a process such as magnetic field heat treatmentin which magnetic field conditions are precisely controlled isnecessary. In contrast, there is no regulation in the magnetic propertyof the second magnetic layer 3 of the embodiment for the above-describedreason, formation is very easy.

Since the memory cell 12 to be written is selected on the basis of theso-called matrix driving method, the magnetic characteristic,dimensions, and the like of the second magnetic layer 3 are set so thatthe magnetization can be inverted only when current is passed in thesame direction to both of the write lines 6X and 6Y, not to one of thewrite lines 6X and 6Y. In the case of giving magnetic anisotropy to thesecond magnetic layer 3, to stabilize the magnetization in a state wherethe magnetization is parallel/anti-parallel with the magnetization ofthe first magnetic layer 1, it is preferable to set the axis of easymagnetization of the second magnetic layer 3 to be parallel with themagnetization pinned direction (the direction of the axis of easymagnetization) of the first magnetic layer 1. Although the write lines6X and 6Y are aligned in the vertical direction in this case, forexample, they may be aligned in parallel in the horizontal direction.

In the case of passing currents in the opposite directions to the writelines 6X and 6Y, setting is made so that the induced magnetic fields arecancelled off each other and a magnetic field necessary for writing isnot generated. Concretely, write currents of the same magnitude arepassed to the write lines 6X and 6Y, and setting is made so that themagnitudes of the induced magnetic fields are equal to each other in thesecond magnetic layer 3.

The toroidal magnetic layer 5 has a cylindrical shape having the axisperpendicular to the drawing sheet of FIG. 3 and includes a part inwhich the write lines 6X and 6Y are parallel with each other. Thetoroidal magnetic layer 5 is made of a magnetic material having highmagnetic permeability, and its sectional shape is a closed loop as shownin the diagram. Consequently, the magnetic fields induced to thecurrents flowing in the write lines 6X and 6Y re-circulates in the layeralong a surface parallel with the section of the toroidal magnetic layer5. As described above, the toroidal magnetic layer 5 has the function ofconfining the magnetic flux of the induced magnetic field in the layerand efficiently inverting the magnetization of the second magnetic layer3. Simultaneously, it has the electromagnetic shielding effect whichprevents a magnetic flux from being leaked to the outside. Since thetoroidal magnetic layer 5 is constructed so as to be in contact with onesurface of the second magnetic layer 3, the magnetic field can be easilytransmitted to the second magnetic layer 3, and the magnetic field canbe applied to the second magnetic layer 3 positioned in proximity withhigh magnetic flux density.

In each of the magnetoresistive devices 12A and 12B, read current flowsfrom the read sensing conductor 11 to the stacked body and passes fromthe toroidal magnetic layer 5 to the substrate 10. Therefore, conductivematerials are used for all of the layers in the stacked body except forthe nonmagnetic layer 2 to which tunnel current is passed, thenonmagnetic conductive layer 4 and the toroidal magnetic layer 5. Forthe first and second magnetic layers 1 and 3, for example, a cobalt ironalloy (CoFe) is used. Other than the cobalt iron alloy, a single cobalt(Co), a cobalt platinum alloy (CoPt), a nickel iron cobalt alloy(NiFeCo), or the like can be used. The nonmagnetic conductive layer 4functions to antiferromagnetic-couple the second magnetic layer 3 andthe toroidal magnetic layer 5. For example, ruthenium (Ru), copper (Cu),or the like is used. For the toroidal magnetic layer 5, iron (Fe),nickel iron alloy (NiFe), Co, CoFe, NiFeCo, or the like can be used. Tomake the magnetic fields generated by the write lines 6X and 6Yconcentrated in the toroidal magnetic layer 5, it is preferable to use amaterial having permeability as high as possible (concretely, thepermeability is 2,000 or higher, more preferably, 6,000 or higher). Thewrite lines 6X and 6Y are made of aluminum (Al), copper (Cu), or analloy of aluminum or copper and are electrically insulated from eachother via an insulating film. The write lines 6X and 6Y may be made oftungsten (W) and one of the above-described materials or may haveanother structure in which titanium (Ti), titanium nitride (TiN), andaluminum (Al) are sequentially stacked.

As will be described in detail later, one of the magnetoresistivedevices 12A and 12B in the memory cell 12 is set to a low resistancestate, and the other is set to a high resistance state to storeinformation. This is for amplifying the difference between outputs fromthe two magnetoresistive devices 12A and 12B and reading the resultant.The magnetoresistive devices 12A and 12B paired have to be manufacturedso as to have the same resistance value, the same magnetic resistancechange rate, and the same magnitude of the inversion magnetic field ofthe second magnetic layer 3.

On the substrate 10 over which the magnetoresistive devices 12A and 12Bare to be formed, an epitaxial layer 9 is formed. On the epitaxial layer9, a conductive layer 8 and an insulating layer 7 are formed. Theconductive layer 8 is constructed by conductive layers 8A and 8Binsulated from each other via the insulating layer 7. Themagnetoresistive devices 12A and 12B are formed on the top face of theconductive layer 8 and the insulating layer 7 and positioned so that atleast part of the formation areas of the magnetoresistive devices 12Aand 12B overlap with the formation areas of the conductive layers 8A and8B. Therefore, the magnetoresistive devices 12A and 12B are joined tothe conductive layers 8A and 8B insulated from each other, respectively,and are electrically insulated from each other. That is, wiring isconducted so that the magnetoresistive devices 12A and 12B areelectrically non-conductive.

The substrate 10 takes the form of an n-type silicon wafer. Generally,the n-type silicon wafer is doped with impurity of P (phosphorus). Asthe substrate 10, a substrate of the n⁺⁺ type obtained byhigh-concentration doping of P (phosphorus) is used. On the other hand,as the epitaxial layer 9, a substrate of the n⁻ type obtained bylow-concentration doping of P (phosphorus) is used. The conductive layer8 is made of a metal. When the epitaxial layer 9 as an n⁻ typesemiconductor and the metal conductive layer 8 come into contact witheach other, a band gap occurs and a Schottky diode is formed. This ishow backflow prevention diodes 13A and 13B in the embodiment are formed.

The diodes 13A and 13B are provided to prevent backflow of read currentfrom the substrate 10 side via the magnetoresistive devices 12A and 12B.The magnetoresistive device 12A and the backflow prevention diode 13Aare insulated from the magnetoresistive device 12B and the backflowprevention diode 13B.

The configuration and operation of a write circuit system in themagnetic memory device will now be described.

Configuration of Write Circuit System

FIG. 4 shows the configuration of the write circuit system of themagnetic memory device. Due to the limited space, the memory cell group140 and the current drives 123 and 133 cannot be drawn. Consequently,the (n)th and (n+1)th configuration units are representatively shown.The X-direction address decoder 121 is connected to the current drive123 ( . . . 123 n, 123 n+1, . . . ) via a write word decode line 16X ( .. . 16Xn, 16Xn+1, . . . ). The Y-direction address decoder 131 isconnected to the current drive 133 ( . . . 133 n, 133 n+1, . . . ) via awrite bit decode line 16Y ( . . . 16Yn, 16Yn+1, . . . ). The X-directionaddress decoder 121 and the Y-direction address decoder 131 transmitselection signals corresponding to address high-order bits input fromthe address buffer 110 to the write word decode line 16X and the writebit decode line 16Y, respectively. By the selection signals, one of thecurrent drives 123 is selected and becomes operable, and one of thecurrent drives 133 is also selected as an object to be driven.

The X-direction current drive 123 and the Y-direction current drive 133are constant current source circuits for supplying current of apredetermined magnitude to the write lines 6X and 6Y, respectively, atthe time of writing data to the memory cell 12. One end of the writeline 6X is connected to a drive point A in the current drive 123, andthe other end is connected to a drive point B. One end of the write line6Y is connected to a drive point A in the current drive 133, and theother end is connected to a drive point B. Current can be supplied inboth directions from the drive point A to the drive point B and from thedrive point B to the drive point A.

The current drives 123 and 133 are controlled to write, according to thedirections of current supplied to the write lines 6X and 6Y, (1) “1” or“0” and (2) in which one of the memory cells 12Ev and 12Od as a pair.The direction of the write current is selected by the data signal XDinand the reference signal XRef in the current drive 123 and is selectedby a data signal YDin and a reference signal YRef in the current drive133. The data signals XDin and YDin are supplied from the write logiccontroller 152 to the current drives 123 and 133 as described above, andthe reference signals XRef and YRed are inversion signals of the datasignals XDin and YDin.

FIG. 5 shows a correspondence table of logic controls performed by thewrite logic controller in this case, and FIG. 6 shows a concrete exampleof the write logic controller. There are four ways to “write data to thememory cells 12Ev and 12Od” as shown in the correspondence table, andone of the four ways is unconditionally determined by the addressselection signal A₀ and the data signal Din. The data signals XDin andYDin in the case of passing current in the direction from the drivepoint A to the drive point B in the current drives 123 and 133 are setto “1”, and the data signals XDin and YDin in the case of passingcurrent in the direction from the drive point B to the drive point A areset to “0”. The write logic controller 152 determines the data signalsXDin and YDin so that four operation patterns of the supply currentdirections in the current drives 123 and 133 correspond to four ways ofcontrols identified by the address selection signal A₀ and the datasignal Din which are input.

Configuration of Current Drives

The action and configuration of the current drives 123 and 133 in theembodiment will now be described. FIG. 7 shows a concrete configurationof the current drive, and FIG. 8 shows a conceptual configurationfocused on the functions.

The current drives 123 and 133 have both of (1) the function as a switchfor controlling the direction of current passed to the write lines 6Xand 6Y, and (2) the function of fixing the current amount to apredetermined value, and can supply stable constant current obtained byeliminating the influence of resistance variations in the write line 6.The (1) function of controlling the direction of current is realized bya current direction controller 64 shown in FIG. 8. The current directioncontroller 64 is constructed by three differential switch pairs; firstand second differential switch pairs 61 and 62 and a differentialcontroller 63 (third differential switch pair).

The first differential switch pair 61 is constructed by switches Q1 andQ2. The switches Q1 and Q2 are provided between the power source Vcc andterminals A and B of the write line 6. When one of the switches Q1 andQ2 is turned and the other is turned off, current from the power sourceVcc is passed to one of the ends A and B. The second differential switchpair 62 is constructed by switches Q3 and Q4. The switches Q3 and Q4 areprovided between the ends A and B of the write line 6 and the ground.When one of the switches Q3 and Q4 is turned on and the other is turnedoff, one of the ends A and B is led to the ground to let the current go.

Therefore, while the switches Q1 and Q4 are closed and the switches Q2and Q3 are open, current flows in the write line 6 in the direction ofthe dotted line. While the switches Q1 and Q4 are open and the switchesQ2 and Q3 are closed, current flows in the write line 6 in the directionof the solid line. Such complementary operations of the first and seconddifferential switch pairs 61 and 62 are controlled by the differentialcontroller 63. The differential controller 63 is constructed by, forexample, switches Q5 and Q6, differentially senses the on/off state ofthe switches Q3 and Q4 and, on the basis of the result of sensing,controls the on/off state of the switches Q1 and Q2, thereby making thetwo differential switch pairs 61 and 62 operate in cooperation with eachother.

The switches Q1 to Q6 correspond to the transistors Q1 to Q6 in theactual circuit of FIG. 7, respectively. To the base terminal of thetransistor Q3, a data signal line 14 (Din) to which a data signal basedon data to be written is input is connected. To the base terminal of thetransistor Q4, a reference signal line 15 (Ref) to which a referencesignal obtained by inverting the data signal is input is connected.

The (2) function of controlling the constant current in the write lineis realized by a current amount controller 65 (refer to FIG. 8). Thecurrent amount controller 65 is provided on the ground side than thewrite line 6 and functions to fix the amount of current flowing out fromthe write line 6. Since the current amount is the current amount in thewrite line 6, current of a constant amount always flows in the writeline 6 irrespective of the resistance value in the write line 6. In aconventional current drive, the current amount control has to beperformed at an ante stage of supplying current to the write line, andthe constant current control which is as perfect as the constant currentcontrol of the present invention has not been realized. In FIG. 8, thecurrent amount controller 65 is constructed by two constant currentsources provided between the switches Q3 and Q4 and the ground. The twoconstant current sources are an expression of an equivalent circuit orthe like in order to give description along a current path. In reality,one constant current circuit commonly connected to the transistors Q3and Q4 may be used.

In FIG. 7, the decode signal voltage input to the transistor Q8, theresistor R4 for current regulation, and the word decode line 16X (bitdecode line 16Y) corresponds to the current amount controller 65. Thatis, it is designed so that the decode signal is set to a predeterminedvoltage at the ante stage of the current drive 123 (133).

The transistors Q7 and Q8 also function as semiconductor switches fordecoding. To the base terminals of the transistors Q7 and Q8 of thecurrent drive 123, the word decode lines 16X ( . . . , 16Xn, 16Xn+1, . .. ) are connected. To the base terminals of the transistors Q8 and Q7 ofthe current drive 133, the bit decode lines 16Y ( . . . , 16Yn, 16Yn+1,. . . ) are connected.

Operation of Current Drive

As a concrete example, the operation performed in the case where thecurrent drive 123 selected by the word decode signal Xn supplies currentto the write line 6Xn from the drive point A to the drive point B willbe described. At this time, a data signal of the “low” level is input tothe data signal line 14, and the reference signal of the “high” level isinput to the reference signal line 15. Therefore, the transistor Q3 isturned off, and the transistor Q4 is turned on.

When the transistor Q4 is turned on, in the transistor Q6, the basevoltage drops and becomes almost the same as the potential of theemitter terminal. Consequently, the transistor Q6 is turned off. Sincethe transistor Q3 is in the off state, in the transistor Q5, a highvoltage relative to that at the emitter terminal is applied to the baseterminal. Consequently, the transistor Q5 is turned on.

When the transistor Q5 is turned on, the base voltage of the transistorQ2 drops. Since the transistor Q6 is in the off state, the base voltageof the transistor Q1 becomes relatively high. As a result, thetransistor Q1 enters the on state in which a larger amount of currentflows, and the transistor Q2 enters the off state in which a smalleramount of current flows. That is, by the influence of the on/offoperation on the transistors Q5 and Q6 exerted on the voltage level atthe base terminal, the transistor Q1 operates to pass a large mount ofcurrent, and the transistor Q2 operates to pass a very small amount ofcurrent.

As a result of the series of operations of the transistors Q1 to Q6,current from the power source Vcc flows on the side of the transistor Q1which is in the on state as one of the transistors Q1 and Q2 and flowsinto the drive point A. Since the transistor Q3 is in the off state, thecurrent flows from the drive point A to the write line 6Xn, flows outfrom the drive point B, passes through the transistor Q4 in the onstate, and flows into the ground side.

That is, in the first differential switch pair, when the transistor Q1is turned on and the transistor Q2 is turned off, the drive point A isselected to the current inflow side of the write line 6Xn. On the otherhand, in the second differential switch pair, when the transistor Q3 isturned off and the transistor Q4 is turned on, the drive point B on theother side is selected to the current outflow side of the write line6Xn. In such a manner, the write current is supplied from the currentdrive 123 to the write line 6Xn in the direction from the drive point Ato the drive point B.

The write current is led to the ground via the transistor Q8 and theresistor R4. The magnitude I of the write current flowing into the pathof the transistor Q4 and the resistor R4 is given by Formula 1 when theresistance value of the resistor R4 is Rc.I(A)=(Vb−φ′)(Volt)/Rc(Ω)   Formula 1

where Vb denotes the voltage level input to the base terminal of thetransistor Q8, and φ′ denotes a forward voltage between the base and theemitter. Since the values are fixed values, it is understood that oncethe resistance value Rc is determined, the current passed becomes afixed value, and the current value is unconditionally determined byusing the resistance value Rc as a parameter. As described above, thevalue of the write current is fixed on the path where it flows from thewrite line 6Xn, so that the write current flows in the write current 6Xnalways with a predetermined value.

On the other hand, to pass the current in the direction from the drivepoint B to the drive point A, it is sufficient to input the data signalof the “high” level to the data signal line 14 and to input thereference signal of the “low” level to the reference signal line 15. Thefirst to third differential switch pairs (transistors Q1 to Q6) switchin the manner opposite to the above case, the write current flows fromthe transistor Q2 to the drive point B, flows out from the drive point Avia the write line 6Xn, and flows in the transistor Q3.

Writing Operation

On the basis of the above, a driving method of the write circuit systemin the magnetic memory device will be described.

First, the information storing method in the memory cell 12 will bedescribed. In the memory cell 12, the magnetization directions of thefirst magnetic layers 1 in the pair of magnetoresistive devices 12A and12B are fixed in the predetermined direction (to the right side in FIGS.11 and 13) but the second magnetoresistive layers 3 are magnetized inanti-parallel with each other. Consequently, in the magnetoresistivedevices 12A and 12B, the combination of the magnetization directions ofthe first and second magnetic layers 1 and 3 are always “anti-parallel,parallel” or “parallel, anti-parallel”. Therefore, by making each of thestates correspond to binary information “0” and “1”. By setting thememory cell 12 to any of the states, information of one bit can bestored in one memory cell 12. When the magnetization directions of thefirst and second magnetic layers 1 and 3 are parallel with each other,the magnetoresistive device 12A (12B) enters a low resistance state inwhich a large tunnel current flows. When the magnetization directionsare anti-parallel with each other, the magnetoresistive device 12A (12B)enters a high resistance state in which only a small tunnel currentflows. That is, one of the magnetoresistive devices 12A and 12B in thepair enters a low resistance state, and the other enters a highresistance state, thereby storing information.

The storage states are written by making the magnetization directions ofthe second magnetic layers 3 of the magnetoresistive devices 12A and 12Banti-parallel with each other. To make the magnetization directionsanti-parallel with each other, currents opposite to each other have tobe passed to the magnetoresistive devices 12A and 12B.

A method of writing information based on the storing method will now bedescribed. First, the address buffer 110 receives voltages of addresssignals input to the external data terminals A0 to A20 and amplifiesthem by the internal buffer. Signals of higher bits are transmitted tothe address decoders 121 and 131 via the address lines 101 and 102,respectively (FIGS. 1 and 4). The address selection signal A₀ as theleast significant bit of the address is transmitted to the write logiccontroller 152 via the group selection signal line 106. The data buffer150 receives voltages of data signals input to the external dataterminals D0 to D7, amplifies them by the input buffer 151, converts theamplified signals to the data signals XDin and YDin in the write logiccontroller 152 to which the address selection signal A₀ is input, andgenerates reference signals XRef and YRef as inversion signals of thedata signals XDin and YDin.

At the time of writing, the address decoders 121 and 131 transmitselection signals of address upper bits which are input from the addressbuffer 110 to the current drives 123 and 133 via the write word decodelines 16X ( . . . 16Xn, 16Xn+1, . . . ) and the write bit decode lines16Y ( . . . 16Yn, 16Yn+1, . . . ), respectively. In each of the currentdrives 123 and 133, the word decode value or the bit decode valuebecomes the “high” level, the transistors Q7 and Q8 are made conductive(FIGS. 4, 7, and the like), and the current drive is selected as anobject to be driven.

From the write logic controller 152, the data signals XDin and YDin areinput to the data signal lines 14 of the current drives 123 and 133, andthe reference signals XRef and YRef are input to the reference signallines 15, respectively. By the operation, in the current drives 123 and133 selected to be driven, the direction of the write current passed tothe write lines 6X and 6Y is determined in accordance with the memorycell 12 to be written and binary information.

In such a manner, the current drives 123 and 133 are driven to supplythe write current in the desired direction to the desired write lines 6Xand 6Y. The memory cell 12 is unconditionally selected, and bit data iswritten in accordance with the direction of the write current.

For example, in the case of writing “1” to the memory cell 12Evbelonging to the memory cell group 12Ev of an even-numbered address inthe corresponding pair of memory cells 12 by using the current drives123n and 133 n, the current drives 123 n and 133 n are driven inaccordance with the logic shown in FIG. 5. That is, as shown in FIG. 10,the current drives 123 n and 133 n operate to pass current in thedirection from the drive point A to the drive point B.

At this time, by the bending of the write line 6Xn, write currents flowwith their directions are aligned in each of the areas of themagnetoresistive devices 12A and 12B of the memory cell 12Ev, and withtheir direction in the magnetoresistive device 12A and that in themagnetoresistive device 12B opposite to each other. By the writecurrent, in the magnetoresistive devices 12A and 12B of the memory cell12Ev, the magnetic fields re-circulating in opposite directions as shownin FIG. 11 are induced to each toroidal magnetic layer 5, and themagnetization directions (that is, the directions of the inducedmagnetic field) in the surface facing the second magnetic layer 3 becomeanti-parallel with each other. The magnetization directions of thesecond magnetic layer 3 of the magnetoresistive devices 12A and 12Benter an anti-parallel state in which they are opposite to each other inaccordance with the direction of the magnetic field supplied from theoutside, and this state is fixed by antiferromagnetic coupling with thetoroidal magnetic layer 5. In this case, the magnetoresistive device 12Ahas high resistance, and the magnetoresistive device 12B has lowresistance.

On the other hand, in the area in each of the magnetoresistive devices12A and 12B on the side of the memory cell 12Od, write currents oppositeto each other flow in the write lines 6Xn and 6Yn. The write currents inopposite directions cancel off the induced magnetic fields, so that datais not written in the magnetoresistive devices 12A and 12B. In such amanner, write currents are supplied simultaneously to the pair of memorycells 12 (12Ev and 12Od) and data is selectively and properly writtenonly to the memory cell 12Ev.

To write “0” into the memory cell 12Ev belonging to the memory cellgroup Ev of the even-numbered address, as shown in FIG. 12, the currentdrives 123 n and 133 n pass currents in the direction from the drivepoint B to the drive point A. That is, the current direction is oppositeto that in the case of writing “1”. At this time as well, on the side ofthe memory cell 12Ev, write currents of the same direction flow in sucha manner that the direction of the current in the magnetoresistivedevice 12A and that in the magnetoresistive device 12B are opposite toeach other. The induced magnetic fields by the write currentsre-circulate in the toroidal magnetic layers 5 as shown in FIG. 13, andthe magnetization directions of the second magnetic layers 3 of themagnetoresistive devices 12A and 12B become anti-parallel with eachother so as to be opposite to each other. In this case, therefore, themagnetoresistive devices 12A and 12B operate as if their positions inthe case of writing “1” are changed, and the magnetoresistive device 12Ahas low resistance, and the magnetoresistive device 12B has highresistance.

In this case as well, in the areas of the magnetoresistive devices 12Aand 12B on the side of the memory cell 12Od, the write currents flow inopposite directions in the write lines 6Xn and 6Yn, so that data is notwritten.

To write “1” in the memory cell 12Od belonging to the memory cell groupOd of the odd-numbered address, as shown in FIG. 14, the current drive123 n passes currents to the write line 6Xn in the direction from thedrive point B to the drive point A. The current drive 133 n passescurrents to the write line 6Yn in the direction from the drive point Ato the drive point B. That is, the current direction is opposite to thatin the case of writing “1”. At this time, as shown in FIG. 11, thewriting operation is performed in such a manner that write currents ofthe same direction flow on the side of the memory cell 12Od, and thedirection of the write current in the magnetoresistive device 12A andthat in the magnetoresistive device 12B are opposite to each other. Onthe side of the memory cell 12Ev, write currents in the oppositedirections flow in the write lines 6Xn and 6Yn and in the areas of themagnetoresistive devices 12A ad 12B, so that no data is written.

To write “0” in the memory cell 12Od belonging to the memory cell groupOd of the odd-numbered address, as shown in FIG. 15, the write currentsare supplied in the directions opposite to those in FIG. 14.Specifically, the current drive 123 n passes currents to the write line6Xn in the direction from the drive point A to the drive point B. Thecurrent drive 133 n passes currents to the write line 6Yn in thedirection from the drive point B to the drive point A. At this time, thewriting operation as shown in FIG. 13 is performed on the side of thememory cell 12Od. At this time as well, on the side of the memory cell12Ev, write currents in the opposite directions flow in the write lines6Xn and 6Yn in the areas of the magnetoresistive devices 12A ad 12B, sothat no data is written.

By controlling the directions of write currents to be passed to the pairof write lines 6Xn and 6Yn as described above, either “1” or “0” iswritten in one of the pair of memory cells 12Ev and 12Od. Although thecase where the write lines 6Xn and 6Yn are selected has been describedhere, information is written in wiring pairs other than the write lines6X and 6Y by a similar driving method. Although the cell state shown inFIG. 11 corresponds to “1” and the cell state shown in FIG. 13corresponds to “0” in the above description, “1” and “0” may correspondto the cell states oppositely.

In this case, the induced magnetic fields in the write lines 6X and 6Yare generated so as to be directed only to the magnetization inversiondirection of the second magnetic layer 3. In the second magnetic layer3, therefore, the magnetization can be inverted in the predetermineddirection by a single-direction magnetic field applied. By theoperation, writing can be performed with reliability. Since the magneticfield components by the write lines 6X and 6Y are in the same directionand confined in the toroidal magnetic layer 5, the intensity of theeffective magnetic field contributing to the inversion of themagnetization of the second magnetic layer 3 becomes higher as comparedwith that in the conventional technique. As a result, the magnetizationof the second magnetic layer 3 can be inverted with sufficient magneticfield intensity, and the magnetizations of the second magnetic layers 3can be aligned in a predetermined direction. Since the induced magneticfields are not leaked to the outside of the device 12A (12B) to bewritten because of the shield effect of the toroidal magnetic layer 5,the possibility that the magnetization direction of the second magneticlayer 3 in the neighboring memory cell 12 is disturbed by an externaldisturbing magnetic field decreases. Information which is once writtencan be prevented from being unexpectedly erased or rewritten.

The configuration and the operation of a read circuit system in themagnetic memory device will now be described.

Configuration of Reading Circuit

FIG. 16 shows a circuit portion corresponding to FIG. 2 of the readcircuit system of the magnetic memory device. FIG. 17 shows a generalcircuit related to reading operation of one of read circuits divided intwo systems for even-numbered addresses and odd-numbered addresses ofmemory cells. As described above, the two circuit systems are similarlyconstructed with respect to the configuration and the operation, so thatone system will be described mainly with reference to FIG. 17.

The read circuit system is a differential amplifier in which each of thememory cells 12 is constructed by a pair of magnetoresistive devices 12Aand 12B. Information in each of the memory cells 12 is read byoutputting the difference between sensing currents passed to themagnetoresistive devices 12A and 12B. The sensing current is currentthat flows from the sense bit lines 21A and 21B to the magnetoresistivedevices 12A and 12B and flows out to a common sense word decode line 31.

In the memory cell group 140, wiring in a matrix is conducted by thesense word decode lines 31 (hereinafter, simply called sense word lines)arranged in the X direction and the pair of sense bit lines 21A and 21Barranged in the Y direction. Each memory cell 12 is disposed in theintersecting position of the word decode line 31 and the bit decode line21. The memory cells 12 connected in parallel with the common sense bitlines 21A and 21B construct a bit line, and the memory cells 12 cascadedto the common sense word line 31 construct a word line. In one memorycell 12, one ends of the magnetoresistive devices 12A and 12B areconnected to the sense bit lines 21A And 21B, respectively, via the readsensing conductors 11, and the other ends are connected to the commonsense word line 31 via the backflow prevention diodes 13A and 13B.

On the one end side (power source Vcc side) of the sense bit lines 21Aand 21B, resistors 23A and 23B for current/voltage conversion(hereinafter, called resistors 23A and 23B) and the collector andemitter of the transistors 22A and 22B are connected in series. The bitdecode line 20 ( . . . , 20 n, 20 n+1, . . . ) is connected to the baseterminal of each of the transistors 22A and 22B, and the transistors 22Aand 22B are opened/closed in accordance with the value (bit decodevalue) of a selection signal input from the bit decode line 20. Senseamplifier input lines 41A and 41B (hereinafter, called input lines 41Aand 41B) are led from nodes provided at the end on the side opposite tothe power source Vcc of the resistors 23A and 23B in the sense bit lines21A and 21B, and are connected to the sense amplifier 132.

The sense amplifier 132 takes the form of a differential amplifier,receives the potential of each of the sense bit lines 21A and 21B,amplifies the potential difference, and outputs the resultant. The senseamplifier 132 has a configuration in which bias resistors 43A and 43Bare commonly provided, and an amplification part 40 as a circuit partother than the bias resistors 43A and 43B is provided per pair of sensebit lines 21A and 21B. The sense amplifier 132 is cascaded to senseamplifier output lines 51A and 51B (hereinafter, called output lines 51Aand 51B). By using the output lines 51A and 51B, the bias resistors 43Aand 43B are commonly used. With the configuration, current consumptionin the plural sense amplifiers 132 is suppressed.

Outputs from the output lines 51A and 51B are transmitted to the readmultiplexer 153 and the output buffer 154 by a read data bus 105. Eachof the pairs of the transistors 22A and 22B, resistors 23A and 23B, andthe sense amplifiers 132 has to have identical characters.

To each of the sense word lines 31, the memory cells 12 arranged in thesame word line are connected (in this case, the backflow preventiondiodes 13A and 13B are disposed between the memory cells 12 and thesense word line 31). The portion between the collector and the emitterof the transistor 33 and a current limiting resistor 34 are connected inseries to the earth side of the sense word line 31. The word decode line30 ( . . . , 30 n, 30 n+1, . . . ) corresponding to the word line Xn onthe base side of the transistor 33. The transistor 33 functions as aswitch which is turned on/off according to the value (bit decode value)of the selection signal supplied from the X-direction address decoder121 to the base.

In the embodiment, the constant current circuit 122 is constructed bythe diode 32, transistor 33, and current limiting register 34. Theconstant current circuit 122 has the function of making current flowingin the sense word line 31 constant. In this case, the diode 32 isobtained by connecting two diodes in series.

Reading Operation

In the magnetic memory device, information written in the memory cell 12is read out as follows.

In each of the memory cells 12 (12Ev and 12Od), the magnetoresistivedevices 12A and 12B are in one of the two ways of anti-parallelmagnetization, and information is stored. A selection signal that isinput to the bit decode line 20 and the word decode line 30 correspondto an upper bit address of the memory cell 12 to be read. That is, whenthe selection signal designates the Yn column and the Xn row, the signalis input to the Yn-th bit decode line 20 n and the Xn-th word decodeline 30 n in both of the memory cell groups Ev and Od. As a result, thememory cell 12Ev in the Yn column and the Xn row in the memory cellgroup Ev and the memory cell 12Od in the Yn column and the Xn row in thememory cell group Od are simultaneously selected. Therefore, thefollowing operation is performed in both of the memory cell groups Evand Od.

When the voltage level in the bit decode line 20 n is set to be “high”,the transistors 22A and 22B become conductive, and sensing current flowsin the Yn-th bit line in the memory cell 12. The sensing current flowsdownward through the sense bit lines 21A and 21B from the power sourceVcc side to the opposite side. On the other hand, when the voltage levelin the word decode line 30 n is set to be “high”, the transistor 33becomes conductive to allow current to flow into the Xn-th word line inthe memory cell 12.

Therefore, the sensing current flows from the Yn-th sense bit lines 21Aand 21B via the magnetoresistive device 12A, backflow prevention diode13A, magnetoresistive device 12B, and backflow prevention diode 13B tothe Xn-th sense word line 31. Further, the sensing current passesbetween the collector and emitter of the transistor 33 as a component ofthe constant current circuit 122, and is passed from the current controlresistor 34 to the ground.

Information is read by detecting the difference between resistancevalues of the magnetoresistive devices 12A and 12B in the memory cell 12as a difference of tunnel currents flowed. The currents flowing in themagnetoresistive devices 12A and 12B are almost equal to the sensingcurrents flowing in the sense bit lines 21A and 21B. The values of thesensing currents are converted to voltages by voltage drops in theresistors 23A and 23B connected in series to the sense bit lines 21A and21B and can be detected. The voltage drops in the resistors 23A and 23Bare taken from input lines 41A and 41B, and the difference between thevoltage drops is detected as a read signal. As described above, bytaking the difference between the output values by using the twomagnetoresistive devices 12A and 12B, a large output value from whichnoise is removed can be obtained from the memory cell 12.

The voltage signals taken from the input lines 41A and 41B are amplifiedby the sense amplifier 132, so that an output of a larger value and anexcellent S/N ratio is obtained. Only sense amplifiers 132 correspondingto the bit line out of the plural sense amplifiers 132 become activesimultaneously with selection of the bit decode line 20. Therefore, onlyoutputs of the corresponding sense amplifiers 132 are transmitted to theoutput lines 51A and 51B.

Outputs of the sense amplifiers 132 (132Ev and 132Od) are supplied viathe output lines 51A and 51B and the read data bus 105 finally to theread multiplexer 153 and the output buffer 154. In the read multiplexer153, one of the output of the sense amplifier 132Ev and the output ofthe sense amplifier 132Od is selected according to the address selectionsignal A₀ input via the group selection signal line 106, and input tothe output buffer 154. The output buffer 154 amplifies the input signalvoltage and outputs the resultant as a binary signal from the externaldata terminals D0 to D7. In such a manner, an output of the memory cell12 to be read is output as a read data signal (Dout) to the outside.

In the reading operation, the magnitude of the sensing current for theselected memory cell 12 is set to be within a predetermined range by theconstant current circuit 122. That is, the current flowing in the senseword line 31 or the total of current flowing in the sense bit lines 21Aand 21B or the magnetoresistive devices 12A and 12B have the value inthe predetermined range. Accordingly, each of the current values isobtained by dividing the current amount normalized to be constant inaccordance with the resistance ratio of the magnetoresistive devices 12Aand 12B. Consequently, even if the resistance values of themagnetoresistive devices 12A and 12B vary, fluctuations in the currentin each of the sense bit lines 21A and 21B are always suppressed withina predetermined range in accordance with the total current value, and astable differential output can be obtained.

The backflow prevention diodes 13A and 13B provided on the current pathsof the magnetoresistive devices 12A and 12B prevent the current fromflowing back from the sense word line 31 to the magnetoresistive devices12A and 12B. Therefore, the path in which a current component flowingback the magnetoresistive device 12A (12B) is generated is interruptedto contribute to improvement in the SIN ratio of a read signal.

As described above, in the embodiment, the loop-shaped write lines 6Xand 6Y are provided separately from the read lines, so that current canbe passed in two ways in both of the write lines 6X and 6Y. Further, thewrite line 6X is bent in a rectangular wave shape to form a parallelportion in which the write lines 6X and 6Y are parallel with each other.The magnetoresistive device 12A (12B) is disposed in the parallelportion, and the parallel magnetic fields generated by the parallelwrite currents are applied to the second magnetic layer 3. Consequently,information is written by applying the magnetic field in a singledirection corresponding to the magnetization inversion direction to thesecond magnetic layer 3. Therefore, the magnetization directions of thesecond magnetic layers 3 can be efficiently aligned to one direction,and the control on the magnetization direction of the magneto-sensitivelayer can be performed more reliably as compared with the conventionaltechnique. At the same time, by inverting the direction of the appliedmagnetic field to the opposite direction, the magnetization direction ofthe second magnetic layer 3 can be also inverted to the oppositedirection almost perfectly, and the tunnel resistance change ratio canbe made higher as compared with the conventional technique.

In the writing method, the magnetization direction of the secondmagnetic layer 3 is forcedly aligned to the direction of the appliedmagnetic field. Therefore, the magnetic property of the second magneticlayer 3 is determined in relation with the magnitude of the appliedmagnetic field. In other words, the second magnetic layer 3 can beformed without considering control on the magnetic property in relationwith the magnitude of the applied magnetic field, the yield inmanufacture of the magnetic memory device is improved, and productivitycan be increased greatly.

Four parallel portions are provided in the pair of write lines 6X and6Y, the magnetoresistive devices 12A and 12B are disposed in the twoparallel portions on the upper side of the write line 6X, therebyforming the memory cell 12Ev of an even-numbered address. Themagnetoresistive devices 12A and 12B are disposed in the two parallelportions on the lower side, thereby forming the memory cell 12Od of anodd-numbered address. Thus, the memory cells 12 read by differentialsensing are integrated efficiently. In the write circuit system, byselecting one of the write lines 6X and 6Y, the write current flowssimultaneously to both of the memory cells 12Ev and 12Od. By selectingthe direction of current in each of the write lines 6X and 6Y in advanceby the write logic controller 152, desired binary information can bewritten only in a selected cell without writing information to the othercell. Specifically, in the selected cell, current flows in parallel inthe write lines 6X and 6Y and the magnetic fields are generated so as toenhance each other. On the other hand, in a not-selected cell, currentsflow in the anti-parallel directions in the write lines 6X and 6Y, andthe induced magnetic fields are cancelled out. Since the magnitudes ofthe write currents flowing in the write lines 6X and 6Y are made equalto each other, the cell selection can be performed with reliability, andthe current drives 123 and 133 can have the same configuration.

The current drives 123 and 133 are constructed in such a manner that theboth ends of the loop-shaped write lines 6X and 6Y are connected to thedrive points A and B, (1) current is passed while changing the directionin accordance with the data signals XDin and YDin, and (2) the amount ofcurrent flowed from the write lines is controlled to be constant. Thus,the current of predetermined magnitude can be supplied in two ways tothe write lines 6X and 6Y irrespective of variations in resistance.Therefore, in the magnetic memory device, the constant current can bealways used to write information to each of the memory cells 12.Reliably writing by an induced magnetic field with sufficient strengthand suppression of a magnetic field leaked to a neighboring memory cell12 within a set range can be performed with excellent controllability,and stable writing operation can be performed. Since (2) it is assuredthat the value of the write current is constant irrespective ofresistance fluctuations and the like of each write line 6, there arealso advantages such that resistance variations in the write line arepermitted (within a certain range), the allowable range of manufactureerrors is widened, and the flexibility of the wiring structure of awrite line increases.

Further, in the magnetic memory device, the read circuit system isconstructed by the circuits of two systems by the memory cell group 12Evand the memory cell group 12Od, the bit decode line 20 and the worddecode line 30 are selected in a manner similar to selection of thewrite lines 6X and 6Y. Thus, the whole device can be controlled on thebasis of an even-numbered address and an odd-numbered address of thememory cell 12. The same drive control circuits can be used for thewriting and reading operations.

Second Embodiment

FIG. 18 shows the configuration of a whole magnetic memory deviceaccording to a second embodiment. In the magnetic memory device, inplace of providing the read multiplexer 153, the X-direction peripheraldrive circuit 120 is provided with a selection decoder switch 124. Theselection decoder switch 124 is provided to receive the addressselection signal A₀ and to select a memory cell to be sensed in order toselect one of the memory cell group 12Ev of an even-numbered address andthe memory cell group 12Od of the odd-numbered address. In the secondembodiment, the same reference numerals are given to components similarto those in the first embodiment and their description will not berepeated.

FIG. 19 is a block diagram showing the configuration of a memory cellgroup, a write circuit system, and a read circuit system. A selectiondecoder switch 124 is expressed as switches 70A and 70B. The switches70A and 70B are paired. The switch 70A is disposed on the side of themagnetoresistive device 12A, and the switch 70B is disposed on the sideof the magnetoresistive device 12B. The switches 70A and 70B select soas to pass sensing current to one of the pair of memory cells 12Ev and12Od. The switches 70A and 70B are arranged in the bit line directionlike switches 70An and 70Bn, switches 70An+1 and 70Bn+1, . . . and areselected in the word line direction of the memory cell 12 by a worddecode value ( . . . , Xn, Xn+1, . . . ).

FIG. 20 is a circuit diagram showing a concrete configuration of theread circuit system corresponding to FIG. 19. The read circuit system ofthe embodiment is obtained by combining the memory cell groups Ev ofeven-numbered addresses and the memory cell groups Od of odd-numberedaddresses into one system. In this case, the selection decoder switch124 is constructed by switches 71, 72, an inverter 73, and the like. Theswitches 71 and 72 correspond to the switches 70A and 70B. The switches71 and 72 are switches of two control commands by a word decode valueand the address selection signal A₀ and select a word line of the memorycell groups Ev and Od as an object to be read.

To the switches 71 ( . . . , 71 n, 71 n+1, . . . ) and switches 72 ( . .. , 72 n, 72 n+1, . . . ), the word decode lines 30 ( . . . , 30 n, 30n+1, . . . ) are connected every pair. All of the switches 71 areconnected to the input line of the address selection signal A₀. All ofthe switches 72 are connected to the input line via the inverter 73 forinverting signals. Further, the switches 71 and 72 are connected to wordselection lines 75 of the memory cell groups Ev and Od, respectively.

The word selection lines 75 are connected to the base terminals oftransistors 74A and 74B of each word line. The collector terminals ofthe transistors 74A and 74B are connected to the sense bit lines 21A and21B and the emitter terminals are connected to the read sensingconductors 11 of the magnetoresistive devices 12A and 12B. In the firstembodiment, the backflow prevention diodes 13A and 13B are providedbetween the magnetoresistive devices 12A and 12B and the sense word line31. In the second embodiment, the transistors 74A and 74B have theblocking functions in place of the backflow prevention diodes 13A and13B by their switch-on/switch-off operations. In the second embodiment,the sense word lines 31 are commonly connected to one constant currentcircuit.

In the read circuit system, information is read as follows.

A selection signal from the X-direction address decoder 121 is input tothe pair of switches 71 and 72 via the word decode line 30. The addressselection signal A₀ is input to the switch 71, and an inversion signalof the address selection signal A₀ is input to the switch 72. By thesignals, only a switch in which both the word decode value correspondingto the address upper bit and the address selection signal A₀corresponding to the address least significant bit are at the “high”level is selected and conducted.

In the word line selected by the switches 71 and 72, the signal voltageof the “high” level is applied to the word selection line 75. As aresult, the transistors 74A and 74B are made conductive to allow thecurrent to flow from the sense bit lines 21A and 21B to thecorresponding sense word line 31.

On the other hand, to the bit decode line 20, a selection signal fromthe Y-direction address decoder 131 is input. A signal of the “high”level is input to the base of each of the transistors connected to thebit decode line 20 in correspondence with the bit decode value, and thetransistors are conducted. Consequently, the sense amplifier 132 of thebit line according to the bit decode value becomes operative and thesensing current is passed to the sense bit lines 21A and 21B.

Therefore, in the circuit system, only one memory cell 12 to be read isidentified by the selection decoder switch 124 as the memory cell 12 tobe sensed, and only one sensing result is output.

In the second embodiment as described above, in place of dividing theread circuit system into two systems and providing the read multiplexer153, one read circuit system is provided and the selection decoderswitch 124 is provided. Consequently, selection of a cell from thememory cells 12Ev and 12Od is performed prior to sensing, and thesensing is performed only the memory cell 12 to be read. Therefore, theread circuit system is controlled by the bit decode value, the worddecode value, and the address selection signal A₀ in a manner similar tothe write circuit system and, since current consumption is reduced, canoperate more efficiently. The other effects are similar to those of thefirst embodiment.

The second embodiment is different from the first embodiment withrespect to the transistors 74A and 74B and the word selection line 75which are provided and also read wiring in the memory cell group 140.However, it is also possible to apply the wiring structure of the firstembodiment almost as it is by replacing the transistor 33 of theconstant current circuit with the switches 71 and 72 of the two controlcommands. The circuit configurations of the foregoing embodiments areconcrete examples. They may be modified without changing the functions,or other circuit configurations may be also employed.

The present invention is not limited to the foregoing embodiments butcan be various modified. For example, in the embodiment, the case offorming four parallel portions by the pair of write lines 6X and 6Y anddisposing the magnetoresistive device 12A (12B) in each of the parallelportions has been described. However, it is sufficient to dispose thefirst and second write lines in the invention so that (1) a parallelportion is formed by bending at least one of the write lines, and (2) atleast one of the write lines is disposed in a loop shape. Wiringstructures other than that in the embodiments can be also employed.

FIGS. 21A and 21B show concrete modifications of the wiring structure ofthe write lines. In FIG. 21A, write lines 81Y in the Y direction aredisposed linearly. By passing currents in opposite directionssimultaneously to the neighboring write lines 81, the write lines can bedriven as if they form a loop. In a manner similar to the embodiment,one memory cell is formed by the magnetoresistive devices 12A and 12B.By enabling each of the write lines 81Y to be selected independently,each of the magnetoresistive devices 12A and 12B can be operated so asto carry one-unit information as a memory cell. In FIG. 21B, the bendingdirection of the write line 81 in the X direction in the upper stage andthat in the lower stage are made opposite to each other. In this case,magnetoresistive devices 12C and 12D neighboring in the verticaldirection along the write line 81Y construct one memory cell.

FIGS. 22A and 22B show another modification. In FIG. 22A, looped writelines 82X and 82Y cross each other. One of the upper and lower stages ofthe write line 82X is bent to form parallel portions. Themagnetoresistive devices 12A and 12B are disposed in the parallelportions. In this case as well, the magnetoresistive devices 12A and 12Bcan be driven as one memory cell. Since the write lines correspond tothe memory cells in a one-to-one manner in both of the X and Ydirections, driving control is easier as compared with that in theforegoing embodiments. Specifically, when each of current drives in theX and Y directions is selected by a word decode value and a bit decodevalue which unconditionally correspond to a memory cell to be writtenand the current supply directions of the current drives are controlledin accordance with data to be written, write current in a predetermineddirection is passed to each of the write lines 82X and 82Y.

FIG. 22B shows a modification of FIG. 22A. A write line 83X is a linearline which is the same as the portion in the lower stage with respect tothe bent portion of the write line 82X.

FIG. 23 shows a modification of the case where the write line is bent ina trapezoid wave shape, not in the rectangular wave shape. Both of writelines 84X and 84Y are bent to form parallel portions in the directionsinclined from the extending directions of the write lines 84X and 84Y.Magnetoresistive devices disposed in the parallel portions are inclined,so that the cell pitch can be narrowed. Although both of the write liens84X and 84Y have a loop shape in the diagram, it is also possible todispose one of the write lines 84X and 84Y linearly and drive the writelines 84X and 84Y in a manner similar to the foregoing othermodifications.

In the foregoing embodiment, both of the current drives 123 and 133 havebeen described as current drives of the present invention. In themagnetic memory device of the invention, however, the current supplycircuit is not always limited to the current drive of the invention.Because of the effects produced by making current constant, it isdesirable to apply the current drive of the present invention. Forexample, the wiring structure of FIG. 22A is more excellent than that ofFIG. 22B for such a reason and from the viewpoint of layout. Withrespect to the current drive of the invention, concrete structures ofcircuit portions corresponding to the current direction controller andthe current amount controller are not limited to those in theembodiments but any structures can be employed as long as the functionsare embodied. Although the current drives 123 and 133 are constructed bybipolar transistors in the embodiment, they can be constructed bysemiconductor devices such as MOSFETs or CMOSs.

The configuration of the magnetoresistive device does not have to be thesame as that in the description of the embodiments. For example, amagnetoresistive device having no toroidal magnetic layer may be alsoused. Although TMR devices are used as the magnetoresistive devices 12Aand 12B in the embodiment, they may be replaced with GMR devices. Theelements in this case can be constructed in a manner similar to themagnetoresistive device 12A (12B) except that the nonmagnetic layer 2 ischanged from the insulating layer to a nonmagnetic metal layer. Asdescribed above, all of known device structures can be applied to themagnetoresistive device of the invention. Any of a CPP (CurrentPerpendicular to the Plane) structure of passing current perpendicularto the stacked face of a magnetic layer and a CIP (Current Flows in thePlane) structure of passing current in parallel with the stacked face ofthe magnetic layer may be employed.

Further, in the foregoing embodiment, the directions of magnetic fieldsapplied to the second magnetic layers 3 are positively aligned at thetime of writing data to the magnetoresistive devices 12A and 12B. Thepresent invention can be effective not only to the case where theapplication magnetic field has only single direction components (themagnetic field components are parallel with each other) but also to thecase where the first and second write lines are provided in parallelwith each other and the magnetic fields induced to the write lines arenot orthogonal to each other. That is, to form two states correspondingto binary signals by inverting the magnetization direction of themagneto-sensitive layer, the application magnetic field has to beinverted by inverting the direction of the write current.Conventionally, when write lines are disposed orthogonal to each other,if current can be passed in two ways to one of the write lines (if onemagnetic field component can be inverted), even if the other currentdirection is fixed (even if the direction of the other magnetic fieldcomponent is fixed), the application magnetic field can form symmetricaltwo states for the reason that the magnetic field components areorthogonal to each other. However, when the write lines are disposed inparallel with each other, if the current direction of one of the writelines is fixed, symmetrical magnetic fields corresponding to two statescannot be generated (refer to FIG. 31). That is, when the first andsecond write lines are provided in parallel with each other, both ofthem have to be constructed so that current flows in two ways.

Although the action and configuration of the read circuit system havebeen also concretely described in the foregoing embodiment, the presentinvention relates to the write circuit system and is not limited by thecircuit configuration, wiring layout, and the like of the read circuitsystem.

As described above, the magnetic memory device of the preset inventionincludes: a read line to which read current is passed; first and secondwrite lines disposed separately from the read line so that write currentcan be passed in two ways to each of the first and second write lines,where a parallel portion in which the first and second write linesextend parallel with each other is formed by bending at least one of thefirst and second write lines; and a magnetoresistive device having amagneto-sensitive layer whose magnetization direction changes accordingto a magnetic field applied, and disposed in the parallel portion. Atleast one of the first and second write lines is formed in a loop shapeso as to include a bent portion and first and second portions connectingthe bent portion and both ends, the magnetization direction of themagneto-sensitive layer changes according to a magnetic field generatedby write current flowing in the parallel portion, and information iswritten. Thus, current can be passed in two ways in both of the firstand second write lines. In the magnetoresistive device, the magneticfields can be generated so as to enhance each other by the write currentsupplied in parallel or anti-parallel with each other from the first andsecond write lines, and the magnetization directions of themagneto-sensitive layer can be changed by the magnetic fields.

In particular, both of the first and second write lines are formed in aloop shape, one of the first and second write lines is bent so that bothof the first and second portions have a rectangular wave shape or atrapezoid wave shape, and the bending direction of the first portion andthat of the second portion coincide with each other, thereby formingfour parallel portions in a pair of first and second write lines. A pairof magnetoresistive devices disposed in the two parallel portionsprovided in the first portion construct a memory cell belonging to afirst group, and a pair of magnetoresistive devices disposed in the twoparallel portions provided in the second portion construct a memory cellbelonging to a second group. With the configuration, irrespective of thearrangement that the memory cell in the first group and the memory cellin the second group are disposed so as to share write lines, bycontrolling the write current directions in two ways, the memory cellscan be written independently of each other. Therefore, whileconstructing memory cells each constructed by a pair of magnetoresistivedevices so as to be drivable, the memory cells can be integratedefficiently.

Further, the magnetic memory device further comprises a write currentdrive circuit including: a current direction controller to which bothends of a write line having a loop shape as one of the first and secondwrite lines are connected and which controls the direction of the writecurrent in the write line in two ways; and a current amount controllerfor controlling the amount of write current in the write line to aconstant value, and supplying the write current to the write line. Whensuch a write current drive circuit is used, irrespective of theresistance value of a current path, the write current having always theconstant magnitude can be supplied to the write line in a predetermineddirection. Therefore, irrespective of fluctuations in the resistancevalues in write lines and the like, stable writing operation can beperformed.

By making magnetic fields generated by the write current supplied to thefirst and second write lines applied to the magneto-sensitive layer soas to be in the same direction in a memory cell to be written, thewriting efficiency can be improved, the magnetization direction of themagneto-sensitive layer can be controlled with reliability, and anexcellent write state can be realized. Moreover, a large read signaloutput can be obtained.

In the method of writing a magnetic memory device of the invention,first and second write lines are provided separately from a read line,and write current can be passed in two ways. At least one of the firstand second write lines is formed in a loop shape including first andsecond portions connecting a bent portion and both ends. A parallelportion in which the first and second write lines extend parallel witheach other is formed by bending at least one of the first and secondwrite lines and making the first and second write lines cross eachother. The magnetoresistive device is disposed in the parallel portion.Write current is supplied to the first and second write lines so thatboth of the write currents flowing in the first and second write linesin the parallel portion are in one of first and second directionscorresponding to write information. By changing the magnetizationdirection of the magneto-sensitive layer by a magnetic field generatedby the write currents, information is written. Thus, the write currentcan be supplied in the direction according to information to be writtenout of the two ways to both of the first and second write lines, and themagnetic fields which can invert the directions can be generated andapplied to the magneto-sensitive layers. Therefore, by generating theapplication magnetic fields so as to enhance each other by the writecurrents in the first and second write lines, the magnetizationdirections of the magneto-sensitive layers can be disposed in twoanti-parallel directions, and binary information can be written in anexcellent write state.

Further, both of the first and second write lines are formed in a loopshape, the first and second portions of one of the first and secondwrite lines are bent in a rectangular wave shape or a trapezoid waveshape so that their bending directions coincide with each other, fourparallel portions are provided in a pair of first and second writelines, a pair of magnetoresistive devices are disposed in two parallelportions provided in the first portion, thereby constructing a memorycell belonging to a first group. A pair of magnetoresistive devices isdisposed in two parallel portions provided in the second portion,thereby constructing a memory cell belonging to a second group. Writecurrent is supplied to the pair of first and second write lines so thatcurrent flows in the same direction in the first and second write linesin both of the two parallel portions and, moreover, current flows inopposite directions in the two parallel portions in a memory cell to bewritten as one of two memory cells belonging to the first and secondgroups. Write current is supplied to the first and second write lines soas to flow in opposite directions in both of the two parallel portionsin the other cells, thereby changing a magnetization direction of eachof the magneto-sensitive layers only in the pair of magnetoresistivedevices in one of the memory cells, and selectively writing information.Proper writing can be performed on a memory cell constructed by a pairof magnetoresistive devices so as to read information in thedifferential amplifying method, and the memory cell in the first groupand the memory cell in the second group disposed on the same write lineare not simultaneously selected but writing can be selectively performedon one of the memory cells.

When information is written by supplying the write current to the firstand second write lines and applying the magnetic fields in the samedirection to the magneto-sensitive layers, the magnetization of themagneto-sensitive layer is inverted to the direction of the appliedmagnetic field. Therefore, writing can be performed efficiently, themagnetization direction of the magneto-sensitive layer can be controlledwith reliability, and an excellent write state can be realized.Accordingly, a large read signal output can be obtained.

Further, when magnitudes of the magnetic fields applied to themagneto-sensitive layer are equalized, it is possible to easily andreliably enable writing in the case where the magnetic fields arealigned in a single direction and enhance each other, and disablewriting in the case where the magnetic fields are in opposite directionsand cancel each other out.

1. A magnetic memory device comprising: a read line to which readcurrent is passed; first and second write lines disposed separately fromthe read line so that write current can be passed in two ways to each ofthe first and second write lines, where a parallel portion in which thefirst and second write lines extend parallel with each other is formedby bending at least one of the first and second write lines; and amagnetoresistive device having a magneto-sensitive layer whosemagnetization direction changes according to a magnetic field applied,and disposed in the parallel portion, wherein at least one of the firstand second write lines is formed in a loop shape so as to include a bentportion and first and second portions connecting the bent portion andboth ends, the magnetization direction of the magneto-sensitive layerchanges according to a magnetic field generated by write current flowingin the parallel portion, and information is written.
 2. A magneticmemory device according to claim 1, wherein the parallel portion isformed by bending one of the first and second portions into arectangular wave shape or a trapezoid wave shape.
 3. A magnetic memorydevice according to claim 1, wherein the parallel portion is formed bybending both of the first and second portions into a rectangular waveshape or a trapezoid wave shape.
 4. A magnetic memory device accordingto claim 3, wherein the direction of bending the first portion and thatof the second portion coincide with each other.
 5. A magnetic memorydevice according to claim 2, wherein a pair of magnetoresistive devicesconstruct one memory cell.
 6. A magnetic memory device according toclaim 1, wherein both of the first and second write lines are formed ina loop shape, one of the first and second write lines is bent so thatboth of the first and second portions have a rectangular wave shape or atrapezoid wave shape, and the bending direction of the first portion andthat of the second portion coincide with each other, thereby formingfour parallel portions in a pair of first and second write lines, a pairof magnetoresistive devices disposed in the two parallel portionsprovided in the first portion construct a memory cell belonging to afirst group, and a pair of magnetoresistive devices disposed in the twoparallel portions provided in the second portion construct a memory cellbelonging to a second group.
 7. A magnetic memory device according toclaim 6, further comprising a write logic controller for receivingaddress information indicating the first or second group to which amemory cell to be written belongs and write information to be written,and selecting the direction of write current supplied to the first andsecond write lines on the basis of the address information and the writeinformation.
 8. A magnetic memory device according to claim 1, furthercomprising a write current drive circuit including: a current directioncontroller to which both ends of a write line having a loop shape as oneof the first and second write lines are connected and which controls thedirection of the write current in the write line in two ways; and acurrent amount controller for controlling the amount of write current inthe write line to a constant value, and supplying the write current tothe write line.
 9. A magnetic memory device according to claim 7,further comprising a write current drive circuit including: a currentdirection controller to which both ends of a write line having a loopshape as one of the first and second write lines are connected and whichcontrols the direction of the write current in the write line in twoways; and a current amount controller for controlling the amount ofwrite current in the write line to a constant value, and supplying thewrite current to the write line, wherein the direction of write currentsupplied to the first and second write lines selected by the write logiccontroller is output as direction control information for controlling acurrent direction to the current direction controller, and the currentdirection controller controls the direction of write current in thewrite line on the basis of the direction control information.
 10. Amagnetic memory device according to claim 8, wherein the currentdirection controller includes: a first differential switch pairconstructed by first and second current switches provided for both endsof the write line and operating so that one of the first and secondcurrent switches is open and the other is close; and a seconddifferential switch pair constructed by third and fourth currentswitches provided in correspondence with the first and second currentswitches, respectively, and operating so that one of the third andfourth current switches is open and the other is close, the firstdifferential switch pair has the function of selecting one of both endsof the write line as a write current inflow side, and the seconddifferential switch pair has the function of selecting the other one ofthe both ends of the write line as a write current outflow side.
 11. Amagnetic memory device according to claim 10, wherein the currentdirection controller includes a differential controller for performing acontrol so that the first and fourth current switches are in the sameopen/close state, and the second and third current switches are in thestate opposite to the state of the first and fourth current switches.12. A magnetic memory device according to claim 5, wherein magneticfields generated by the write current flowing in the parallel portion ofthe first and second write lines are applied to the magneto-sensitivelayer so as to be in the same direction in the memory cell to bewritten.
 13. A magnetic memory device according to claim 12, wherein themagnetoresistive device is disposed in an area where a magnetic field isgenerated only in a direction orthogonal to the parallel portion, in theparallel portion.
 14. A magnetic memory device according to claim 1,wherein the magnetoresistive device further comprises a stacked bodyincluding the magneto-sensitive layer, and an toroidal magnetic layer isprovided on one of the faces of the stacked body, the toroidal magneticlayer using a direction along the stacked face as an axial direction,and the parallel portion of the first and second write lines penetratingthe toroidal magnetic layer along the axial direction.
 15. A magneticmemory device according to claim 1, wherein magnitudes of the magneticfields generated by the write current supplied to the first and secondwrite lines are equal to each other.
 16. A method of writing a magneticmemory device comprising: a read line to which read current is passed;first and second write lines extending so as to cross each other, and amagnetoresistive device having a magneto-sensitive layer whosemagnetization direction changes according to a magnetic field generatedby write current supplied to the first and second write lines,comprising the steps of: disposing the first and second write linesseparately from the read line and enabling write current to be passed intwo ways; forming at least one of the first and second write lines in aloop shape including first and second portions connecting a bent portionand both ends; providing a parallel portion in which the first andsecond write lines extend parallel with each other by bending at leastone of the first and second write lines and making the first and secondwrite lines cross each other; disposing the magnetoresistive device inthe parallel portion; supplying write current to the first and secondwrite lines so that both of the write currents flowing in the first andsecond write lines in the parallel portion are in one of first andsecond directions corresponding to write information; and writinginformation by changing the magnetization direction of themagneto-sensitive layer by a magnetic field generated by the writecurrents.
 17. A method of writing a magnetic memory device according toclaim 16, wherein two magnetoresistive devices are disposed in a pair ofthe parallel portions, write current is supplied to the first and secondwrite lines so that the directions coincide in each of the pair ofparallel portions and the directions in the pair of parallel portionsare opposite to each other, thereby changing the magnetizationdirections of magneto-sensitive layers of the two magnetoresistivedevices so as to be anti-parallel with each other, and information iswritten by using the two magnetoresistive device as one memory cell. 18.A method of writing a magnetic memory device according to claim 17,wherein both of the first and second write lines are formed in a loopshape, the first and second portions of one of the first and secondwrite lines are bent in a rectangular wave shape or a trapezoid waveshape so that their bending directions coincide with each other, fourparallel portions are provided in a pair of first and second writelines, a pair of magnetoresistive devices are disposed in two parallelportions provided in the first portion, thereby constructing a memorycell belonging to a first group, a pair of magnetoresistive devices aredisposed in two parallel portions provided in the second portion,thereby constructing a memory cell belonging to a second group, writecurrent is supplied to the pair of first and second write lines so thatcurrent flows in the same direction in the first and second write linesin both of the two parallel portions and, moreover, current flows inopposite directions in the two parallel portions in a memory cell to bewritten as one of two memory cells belonging to the first and secondgroups, and write current is supplied to the first and second writelines so as to flow in opposite directions in both of the two parallelportions in the other cells, thereby changing a magnetization directionof each of the magneto-sensitive layers only in the pair ofmagnetoresistive devices in one of the memory cells, and selectivelywriting information.
 19. A method of writing a magnetic memory deviceaccording to claim 16, wherein write current is supplied to a write lineformed in a loop shape as one of the first and second write lines whilecontrolling the direction of write current by selecting one of both endsas a write current inflow side and selecting the other end as an outflowside, and controlling so that the write current flows on the write lineswith a predetermined current value.
 20. A method of writing a magneticmemory device according to claim 16, wherein information is written bysupplying write current to the first and second write lines and applyingmagnetic fields in the same direction to the magneto-sensitive layers.21. A method of writing a magnetic memory device according to claim 20,wherein magnitudes of the magnetic fields applied to themagneto-sensitive layer are equalized.